Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 7
Platform Design Guide
Intel Confidential
Table 8-4. USB Channel Routing Guidelines..............................................................................................96
Table 8-5. USBRBIASP/ USBRBIASN Routing Guidelines........................................................................ 97
Table 8-6. GBE Transmitter Routing Guidelines.......................................................................................101
Table 8-7. GBE RX Routing Guidelines.................................................................................................... 102
Table 8-8. Expansion Bus Topology for EXP_CS[3:0]B ...........................................................................104
Table 8-9. Expansion Address/Data Bus Star Topology ..........................................................................105
Table 8-10. Data Bus_A Topology list ......................................................................................................106
Table 8-11. Expansion Bus Topology for EXP_CS[3:0]B .........................................................................107
Table 8-12. I2C interconnection list ..........................................................................................................114
Table 8-13. UART0_RXD signal Topology ...............................................................................................116
Table 8-14. UART0_DSRB signal Topology.............................................................................................117
Table 8-15. GPIO Interface list .................................................................................................................119
Table 8-16. SPI Serial Interface Interconnects .........................................................................................120
Table 8-17. SPI SPI_MISO signal Topology list .......................................................................................121
Table 8-18. SPI_MOSI and SPI_SCK signal Topology list....................................................................... 122
Table 8-19. SPI_SS signal Topology list...................................................................................................123
Table 8-20. Smart Card Interface External Signals .................................................................................. 124
Table 8-21. SC0_INS_GP[7] and SC1_INS_GAP[11] Signal Topology List ............................................125
Table 9-1. Video Input Mode Description..................................................................................................127
Table 9-2. HDVCAP Signal Length Table................................................................................................. 128
Table 9-3. HDVCAP Signal Length Table................................................................................................. 129
Table 10-1. CK505 Clock Routing Guidelines ..........................................................................................133
Table 10-2. IDT6V49061 Clock Routing Guidelines .................................................................................134
Table 10-3. IDT6V49061 Clock Routing Guidelines .................................................................................135
Table 10-4. Audio_clk Signal Topology List..............................................................................................136