Specifications

60 Intel

Atom™ processor CE4100 Ref# 420826

Platform Design Guide

Intel Confidential

5.6.2 DDR2 Guidelines for x8 Devices

5.6.2.1 Clock Signals – CLK, CLKB

Table 5-23. Clock Signals – DDRA_CLK/CLKB, DDRB_CLK/CLKB,

Parameter Routing Guidelines

Signal Group CLK

Reference Plane

Recommended Layer

Route over unbroken power plane or ground plane

Micro-strip

Breakout Trace Width and spacing 4 mils x 3.5 mils

Trace Impedance 100 Ω +/- 10%

Trace Spacing (trace edge to edge) • Within pair =7 mils, which might be different based on different stack-

• > 20 mils from any other signals

Parallel Termination 50 Ω +/- 5% single ended terminal to Vtt from CLK_P and Clk_N

respectively

CLK/CLKB Length Matching Match within +/- 0.025”. All the length matching is for board only. Package

length does not need be considered

Number of Vias • Maximum of 2 per trace

Routing Notes: Route as a differential Pair

• Use the LA or other debug headers of type SMD pads if needed. LA

headers can be on the FLY nets.

Figure 5-10. DDR2 Memory Clock Topology

TL1

TL2 TL3

TL3

TL4

SDV

SDRAM1 SDRAM2

SDRAM3

SDRAM4

Termination

LAI