Specifications

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6 Intel

Atom™ processor CE4100 Ref# 420826

Platform Design Guide

Intel Confidential

List of Tables

Table 1-1. Related Documents ...................................................................................................................12

Table 1-2. Acronyms and Terminology....................................................................................................... 15

Table 3-1. 4-layer Board Impedance Target Example................................................................................ 26

Table 3-2. Additional Impedance Requirements Example..........................................................................26

Table 4-1. Decoupling Example..................................................................................................................29

Table 4-2. Layout Recommendations for RESET_INB...............................................................................33

Table 4-3. Layout Recommendations for SYS_PWR_GOOD ....................................................................33

Table 5-1. DDR2 DRAMComponent Organization .....................................................................................42

Table 5-2. DDR3 DRAMComponent Organization .....................................................................................42

Table 5-3. DDR2 Pins .................................................................................................................................43

Table 5-4. Memory Interface Package Lengths.......................................................................................... 44

Table 5-5. Clock Signals – DDRA_CLK/CLKB, DDRB_CLK/CLKB............................................................46

Table 5-6. DDR3 Memory Clock Topology Table ....................................................................................... 47

Table 5-7. Address, Command, and Control ..............................................................................................47

Table 5-8. DDR3 Address, Command, and Control Topology Table .........................................................48

Table 5-9. Data and Strobe Signals – DQ/DM/DQS...................................................................................49

Table 5-10. DDR3 DQ/DM/DQS Topology Table .......................................................................................50

Table 5-11. Clock Signals – DDRA_CLK/CLKB, DDRB_CLK/CLKB .........................................................50

Table 5-12. DDR3 Memory Clock Topology Table ..................................................................................... 51

Table 5-13. Address, Command, and Control ............................................................................................52

Table 5-14. DDR3 Address, Command, and Control Topology Table .......................................................53

Table 5-15. Data and Strobe Signals – DQ/DM/DQS.................................................................................54

Table 5-16. DDR3 DQ/DM/DQS Topology Table .......................................................................................54

Table 5-17. Clock Signals – DDRA_CLK/CLKB, DDRB_CLK/CLKB .........................................................55

Table 5-18. DDR2 Memory Clock Topology Table ..................................................................................... 56

Table 5-19. Address, Command, and Control ............................................................................................56

Table 5-20. DDR2 Address, Command, and Control Topology Table .......................................................57

Table 5-21. Data and Strobe Signals – DQ/DM/DQS.................................................................................58

Table 5-22. DDR2 DQ/DM/DQS Topology Table .......................................................................................59

Table 5-23. Clock Signals – DDRA_CLK/CLKB, DDRB_CLK/CLKB, ........................................................60

Table 5-24. DDR2 Memory Clock Topology Table ..................................................................................... 61

Table 5-25. Address, Command, and Control ............................................................................................62

Table 5-26. DDR2 Address, Command, and Control Topology Table .......................................................63

Table 5-27. Data and Strobe Signals – DQ/DM/DQS.................................................................................64

Table 5-28. DDR2 DQ/DM/DQS Topology Table .......................................................................................64

Table 6-1. Video DAC Signals ....................................................................................................................67

Table 6-2. HDMI Transmitter Routing Guidelines for the 1080 Stack-up ...................................................76

Table 7-1. I

S Audio Input Interconnects ....................................................................................................85

Table 7-2. I2S Audio Input Interconnects....................................................................................................86

Table 7-3. S/PDIF Output Interconnects..................................................................................................... 87

Table 8-1. Serial ATA Differential Pair Routing Guidelines for the 1080 Stack-up..................................... 91

Table 8-2. AC Coupling Capacitor ..............................................................................................................92

Table 8-3. SATA_RBIAS Routing Guidelines for the 1080 Stack-up..........................................................92