Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 57
Platform Design Guide
Intel Confidential
Figure 5-8. DDR2 Address, Command and Control Topology with Two Loads
Table 5-20. DDR2 Address, Command, and Control Topology Table
Traces Description Layer Min
Length
MaxLength Trace Width Spacing
TL1 Breakout Micro strip 0.05" 0.5" 4 Mils >=4 Mils
TL2 Lead-in Micro strip 0.5" 2" 4 Mils >=10 Mils
TL3 Breakout Micro strip 0.05" 0.5" 4 Mils >=4 Mils
TL4 T branch Micro strip 0.1" 0.6" 4 Mils >=10 Mils
TL5 Device Breakout Micro strip 0.05" 0.15" 4 Mils >=4 Mils
Notes:
• CMD/ADDR routing should be length matched to CLK within +/-0.75”.
• T branches should be length matched within 5mils.
• Length of T branch should not exceed 0.75”