Specifications

56 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
Table 5-18. DDR2 Memory Clock Topology Table
Traces Description Layer
Min
Length
Max
Length
Trace
Width Spacing
Spacing
to
nearest
signals
TL1 Breakout Micro strip 0.05" 0.5" 4 Mils 3.5 Mils
TL2 Lead-in Micro strip 1" 2.5" 4 Mils 7 Mils >20 Mils
TL3 Device 1 stub Micro strip 0.05" 0.25" 4 Mils 3.5 Mils
TL4 T line Micro strip 0.05" 1" 4 Mils 7 Mils >20 Mils
TL5 Device 2 stub Micro strip 0.05" 0.25" 4 Mils 3.5 Mils
TL6 T line Micro strip 0.05" 1" 4 Mils 7 Mils > 20 Mils
5.6.1.2 Address, Command and Control
Table 5-19. Address, Command, and Control
Parameter Routing Guidelines
Signal Group Address / Command / Control
Reference Plane
Recommended Layer
Route over unbroken power plane or ground plane
Micro-strip
Breakout Trace Width and spacing 4 mils x 4 mils
Trace Impedance 55 Ω +/- 10%
Trace Spacing (trace edge to
edge)
• Within group >10 mils
• > 20 mils from any other Clock/DQ/DQS groups
Parallel Termination 60 Ω +/-5% terminated to Vtt (recommended termination scheme) OR
Split Termination of 100 Ω +/-10% terminated to Vcc & 100 Ω +/- 10%
terminated to ground.
Termination Resistance DDR2: 120 Ω for CKE/ODT/RST
90 Ω for CMD/ADDR
Trace Length Matching Match CLK signals within +/- 0.75”. All the length matching is for board only.
Package length does not need be considered.
Number of Vias • Maximum of 4
Routing Notes: • Use the LA or other debug headers of type SMD pads. LA headers can be
on the FLY nets.
The VREF, which is 1/2 of VCC1P8_DDR, termination stubs can be placed either on the stubs
or on the fly traces. Termination packs should be either individual or X4 resistor packs.
Resistor packs, like X8 or more, should not be used.