Specifications

54 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
5.5.2.3 Data and Data Strobe Signals – DQ/DM/DQS
Table 5-15. Data and Strobe Signals – DQ/DM/DQS
Parameter Routing Guidelines
Signal Group DQ/DM/ DQS
Reference Plane
Recommended layer
Route over unbroken ground plane.
Micro-strip routing.
Breakout width and spacing 4 mils width on 4mils spacing
Trace Impedance 55 Ω +/- 10%
Trace Spacing (Edge to edge) Within group (byte lane) >=16 mils for DDR3-1333.
>20 mils from any other clock/CMD/Control/DQ/DQS groups
Termination No External Termination required.
Recommended ODT = 60Ω
DQ to DQS length match Match all DQs within same group (byte lane) to its DQS pair within +/-
0.1”.
DQS intra pair length match Match DQSpositive to negative within 0.025”.
DQS to CLK length match Match within +/-1.35”. All length match data is for overall Platform
(package + board) length match.
Number of Vias Maximum of 3
Routing notes Use the LA or other debug headers of type SMD pads. LA headers can
be on the FLY nets.
Figure 5-6. DDR3 DQ/DM/DQS Topology
TL1
TL2
TL3
SDV
SDRAM1
LAI
Table 5-16. DDR3 DQ/DM/DQS Topology Table
Traces Description Layer
Min
Length
Maximum
Length
Trace
Width
Spacing
TL1 Breakout Micro strip 0.05" 0.5" 4 Mils >=4 Mils
TL2 Lead-in Micro strip 0.5" 3.3" 4 Mils >=16 Mils
TL3 Breakout Micro strip 0.05" 0.5" 4 Mils >=4 Mils
Notes:
DQ/DQS is point to point topology, needs to be matched within same byte, and LAI header should be placed
closer to memory chip for better writing signal quality.