Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 53
Platform Design Guide
Intel Confidential
Table 5-14. DDR3 Address, Command, and Control Topology Table
Traces Description Layer
Min
Length
Maximum
Length
Trace
Width Spacing
TL1 Breakout Micro strip 0.05" 0.5" 4 Mils >=4 Mils
TL2 Lead-in Micro strip 0.5" 1.3" 4 Mils >=10 Mils
TL3 Breakout Micro strip 0.05" 0.5" 4 Mils >=4 Mils
TL4 Between Devices Micro strip 0.1" 0.8" 4 Mils >=10 Mils
TL5 Device Breakout Micro strip 0.05" 0.2" 4 Mils >=4 Mils
Notes:
• CMD/ADDR routing should be length matched to CLK routing within +/-0.25” at each device.
• LAI header could be placed closer to the first memory device