Specifications

52 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
5.5.2.2 Address, Command and Control
Table 5-13. Address, Command, and Control
Parameter Routing Guidelines
Signal Group Address / Command / Control
Reference Plane
Recommended Layer
Route over unbroken power plane or ground plane
Micro-strip
Breakout Trace Width and
spacing
4 mils x 4 mils
Trace Impedance 55 Ω +/- 10%
Trace Spacing (trace edge to
edge)
• Within group >10 mils
• > 20 mils from any other Clock/DQ/DQS groups
Parallel Termination 60 Ω +/-5% terminated to Vtt (recommended termination scheme)
OR
Split Termination of 100 Ω +/-10% terminated to Vcc & 100 Ω +/- 10%
terminated to ground
Termination Resistance DDR3: 60 Ω for CMD/ADDR
90 Ω for CKE/ODT/RST
Length Matching to CLK Match CLK/CLKB signals within +/- 0.25”. All length match data is for overall
Platform (package + board) length match.
Number of Vias • Maximum of 6 per trace
Routing Notes: • Use the LA or other debug headers of type SMD pads. LA headers can be
on the FLY nets.
The VREF, which is 1/2 of VCC1P5_DDR (VCC1P8_DDR for DDR2), termination stubs can be
placed either on the stubs or on the fly traces. Termination packs should be either
individual or X4 resistor packs. Resistor packs, like X8 or more, should not be used.
Figure 5-5. DDR3 Address, Command and Control Topology with Four Loads
TL1
TL2
TL3
TL4
TL4
TL4
TL4
TL5
TL5
TL5
TL5
SDV
SDRAM1
SDRAM2
SDRAM3
SDRAM4
Termination
LAI