Specifications

50 Intel

Atom™ processor CE4100 Ref# 420826

Platform Design Guide

Intel Confidential

Table 5-10. DDR3 DQ/DM/DQS Topology Table

Traces Description Layer

Min

Length

Max

Length

Trace

Width Spacing Notes

TL1 Breakout Micro strip 0.05” 0.5” 4 Mils >=4 Mils

TL2 Lead-in Micro strip 1” 3.5” 4 Mils >=16 Mils

TL3 Memory Breakout Micro strip 0.05” 0.5” 4 Mils >=4 Mils

TL4* LA Breakout Micro strip 0” 0.1” 4 Mils >=16 Mils OPTIONAL*

5.5.2 DDR3 Guidelines for x8 Devices

5.5.2.1 Clock Signals – CLK, CLKB

Table 5-11. Clock Signals – DDRA_CLK/CLKB, DDRB_CLK/CLKB

Parameter Routing Guidelines

Signal Group CLK

Reference Plane

Recommended Layer

Route over unbroken power plane or ground plane

Micro-strip

Breakout Trace Width and spacing 4 mils x 3.5 mils

Trace Impedance 100 Ω +/- 10%

Trace Spacing (trace edge to edge) • Within pair =7 mils, which might be different based on different stack-

• > 20 mils from any other signals

Parallel Termination 50 Ω +/- 5% single ended terminal to Vtt from CLKand ClkB respectively.

CLK/CLKB Length Matching Match CLK intra pair within +/- 0.025”. All length match data is for overall

Platform (package + board) length match.

Number of Vias • Maximum of 2 per trace

Routing Notes: Route as a differential Pair

• Use the LA or other debug headers of type SMD pads if needed. LA

headers can be on the FLY nets.

Figure 5-4. DDR3 Memory Clock Topology

TL1

TL2 TL3

TL3

TL4

SDV

SDRAM1 SDRAM2

SDRAM3

SDRAM4

Termination

LAI