Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 49
Platform Design Guide
Intel Confidential
5.5.1.3 Data and Data Strobe Signals – DQ/DM/DQS
Table 5-9. Data and Strobe Signals – DQ/DM/DQS
Parameter Routing Guidelines
Signal Group Source Synchronous [ DQ/DM/DQS ]
Reference Plane Micro-strip routing: Route over unbroken ground plane.
Breakout width and spacing 4 mils width on 4mils spacing
Trace Impedance 55 Ω +/- 10%
Trace Spacing within byte lane
(Edge to edge)
4 mils spacing in breakout regions.
>16 mils. Between all DQ Signals.
>20 mils. must be maintained from other signals or vias, for example DQ to
DQS, DQ to CLK/CMD etc.
Trace Spacing between byte lanes
(Edge to edge)
Trace spacing > 20mils, and coupling trace length < 0.5”. This requirement
is to avoid excessive all-phase crosstalk. For the breakout area, 20-mils
spacing is hard to achieve, so keep the coupling length at breakout as short
as possible.
Breakout Trace Length (TL1)
Lead-in Trace Length (TL2)
Lead-in to LA Connector (TL3)
≤ 0.5”
1.0” to 3.5”
0.025” to 0.1” (Optional Debug connector)
Termination No External Termination required. Internal ODT
DQS intra pair Length Match with-in +/- 0.025”
DQS to CLK Length Match DQS pairs being routed within +/- 1.35” of its reference CLK for each
memory device. All length match data is for overall Platform (package +
board) length match.
DQ/DM to DQS within byte group +/- 100mils
Number of Vias 3 (There must be an equal number of vias between DQ/DM and its
respective DQS signal)
Routing Recommendations Route all signals within a byte group (DQS, DQ / DM of one byte group) on
the same layer.
Figure 5-3. DDR3 DQ/DM/DQS Topology
TL1
TL3
TL2
Break
Out
Lead in
Memory
Break out
LA Probe
Connector
Breakout
LA Probe
TL4