Specifications

48 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
The VREF, which is 1/2 of VCC1P5_DDR (VCC1P5_DDR for DDR2), termination stubs can be
placed either on the stubs or on the fly traces. Termination packs should be either individual
or X4 resistor packs. Resistor packs, like X8 or more, should not be used.
Figure 5-2. DDR3 Address, Command and Control Topology with Two Loads
Table 5-8. DDR3 Address, Command, and Control Topology Table
Traces Description Layer Min
Length
Max
Length
Trace
Width
Spacing within Group
TL1 Breakout Micro strip 0.05" 0.5" 4 Mils >=4 Mils
TL2 Lead-in Micro strip 0.5" 2" 4 Mils >=10 Mils
TL3 Breakout Micro strip 0.05" 0.5" 4 Mils >=4 Mils
TL4 T branch Micro strip 0.1" 0.2" 4 Mils >=10 Mils
TL5 Device Breakout Micro strip 0.05" 0.15" 4 Mils >=4 Mils
Notes:
• CMD/ADDR routing should be length matched to CLK_P/N routing within +/-0.5-to-0.6” for DDR3.
• T branches should be length matched within 5mils.
• Length of T branch should not exceed 0.25” for DDR3.