Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 47
Platform Design Guide
Intel Confidential
Table 5-6. DDR3 Memory Clock Topology Table
Traces Description Layer
Min
Length
Max
Length
Trace
Width Spacing
Spacing
to
nearest
signals
TL1 Breakout Micro strip 0.05" 0.5" 4 Mils 3.5 Mils
TL2 Lead-in Micro strip 1" 2.5" 4 Mils 7 Mils >20 Mils
TL3 Device 1 stub Micro strip 0.05" 0.25" 4 Mils 3.5 Mils
TL4 T line Micro strip 0.05" 1" 4 Mils 7 Mils >20 Mils
TL5 Device 2 stub Micro strip 0.05" 0.25" 4 Mils 3.5 Mils
TL6 T line Micro strip 0.05" 1" 4 Mils 7 Mils > 20 Mils
5.5.1.2 Address, Command and Control
Table 5-7. Address, Command, and Control
Parameter Routing Guidelines
Signal Group Address / Command / Control
Reference Plane
Recommended Layer
Route over unbroken power plane or ground plane
Micro-strip
Breakout Trace Width and spacing 4 mils x 4 mils
Trace Impedance 55 Ω +/- 10%
Trace Spacing (trace edge to
edge)
• Within group >10 mils
• > 20 mils from any other Clock/DQ/DQS groups
Termination Resistance DDR3: 90 Ω for CMD/ADDR
90 Ω for CKE/ODT/RST
Length Matching To CLK Match Address, Command, and Control to CLK signals within +/- 0.5”/0.6”. All
length match data is for overall Platform (package + board) length match.
Number of Vias • Maximum of 3
Routing Notes: • Use the LA or other debug headers of type SMD pads. LA headers can be
on the FLY nets.
Note: Within +/-0.5” is an Intel preference rule to guarantee enough margin for different
DDR3 brands. If the designer finds it difficult to satisfy the 0.5” rule, due to board
compatibility and manufactory limitation, a tolerance within +/- 0.6” is acceptable. The
designer must make sure the total trace length (Package + Board) is within +/- 0.6”.