Specifications

46 Intel

Atom™ processor CE4100 Ref# 420826

Platform Design Guide

Intel Confidential

5.5 DDR3 Design Topologies and

Routing Guidelines

5.5.1 DDR3 Guidelines for x16 Devices

5.5.1.1 Clock Signals – CLK, CLK_B

Table 5-5. Clock Signals – DDRA_CLK/CLKB, DDRB_CLK/CLKB

Parameter Routing Guidelines

Signal Group CLK

Reference Plane

Recommended Layer

Route over unbroken power plane or ground plane

Micro-strip

Breakout Trace Width and spacing 4 mils x 3.5 mils

Trace Impedance 100 Ω +/- 10%

Trace Spacing (trace edge to edge) • Within pair =7 mils, which might be different based on different stack-

• > 20 mils from any other signals.

Parallel Termination 50 Ω +/- 5% single ended terminal to Vtt from CLK and CLKB respectively.

Note: if there is no Vtt, then parallel termination is 100 Ω.

CLK to CLKB length match Match within +/- 0.025” . All length match data is for overall Platform

(package + board) length match.

Number of Vias • Maximum of 3

Routing Notes: Route as a differential Pair

• Use the LA or other debug headers of type SMD pads if needed. LA

headers can be on the FLY nets.

Figure 5-1. DDR3 Memory Clock Topology