Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 43
Platform Design Guide
Intel Confidential
5.2 DDR2/DDR3 Pin Descriptions
Table 5-3 provides a summary of the signal pins specified by the DDR2/DDR3 protocol. For
detailed description of pins and DDR2/DDR3 protocol, refer to the JESD79-2/3 DDR2/DDR3
SDRAM specification.
Table 5-3. DDR2 Pins
Pin Name Direction Number
of pins
Description
DDR_CK[1:0] O 2
DDR_CKB[1:0] O 2
Differential Clock
DDR_MA[14:0] O 15 Address (multiplexed row and column address)
DDR_BS[2:0] O 3 Bank Select
DDR_RASB O 1 Row Address Strobe
DDR_CASB O 1 Column Address Strobe
DDR_WEB O 1 Write Enable
DDR_CSB O 1 Chip Select (used for selecting a rank)
DDR_CKE O 1 Clock Enable
DDR_ODT O 1 On Die Termination
DDR_DQ[31:0] I/O 32 Data
DDR_DM[3:0] O 8 Data Mask
DDR_DQS[3:0] I/O 4
DDR_DQSB[3:0] I/O 4
Differential Data Strobe
DDR_RESETB O 1 Active Low Asynchronous Reset
5.3 Decoupling Recommendations
When designing a board, the following decoupling recommendations should be followed.
Note
These decoupling recommendations are for the Intel
®
Atom™ processor CE4100 pins.
• Place the multiple capacitors in parallel to get the desired value of capacitance and ESL.
• Capacitors should be mounted as close to the processor as possible. They should be no
further than 10mm from the edge of the processor package for each DDR2 channel.
• Decoupling capacitors should be placed near Memory Clock reference layer changes.
This can be done by adding a 0.1μF capacitor between DDR Power and Ground where
each Memory Clock trace changes reference layers.