Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 39
Platform Design Guide
Intel Confidential
4.7 Expansion Bus Strapping Design
Topology
The Expansion bus interface needs to be designed for strapping purposes at the beginning
of system power up. During system power up, this interface can be used as a
communication interface between the SOC and NOR flash or between the SOC and high
definition video capture.
4.7.1 Design Example One
This design topology is used on the Intel innovation model reference design board.
CE4100 PKG
NOR or
other
devices
• Based on the design request, usingRpu or Rpd is to set the strap value to be “1” or “0”;
Rpu = 7.5KΩ, Rpd = 4.7KΩ.
• This topology was simulated and determined that there was no significant effect to
signal quality during normal signal switching.