Specifications

38 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
Strap Name Pin Name Description
DDR_SPEED EXP_ADDR[8:6] Define DDR2/3 Frequency:
000: DDR3-800 Supported
001: DDR3-1066 Supported
010: DDR3-1333 Supported
011: Reserved
100: DDR2-800 Supported
101: Reserved
110: Reserved
111: Reserved
BOOT_WIDTH EXP_ADDR[9] Defines width of flash
0: x8 flash
1: x16 flash
NAND_BOOT EXP_ADDR[10] Enable boot from NAND flash
0: Normal operation
1: Boot from NAND flash
NAND_NUM_ADDR_CYCLES EXP_ADDR[11] Determines whether NAND requires 4-cycle or 5-cycle
addressing
0: four address cycles
1: five address cycles
GBE_CLK_SRC_SEL EXP_ADDR[12] Select between external GBE clock from GBE PHY and
internal GBE clock from HPLL:
0: Select external clock from GBE PHY
1: Select internal clock
27M_DIR_SEL EXP_ADDR[13] Define pin direction for CLK_27M pin
0: 27M Clock pin is output (driven from internal DDS)
1: 27M Clock pin is input (driven from external PLL)
EXP_BOOT_ACCEL_DIS EXP_ADDR[14] Control caching of NOR flash during boot:
0: Enable NOR caching feature (boot acceleration)
1: Disable NOR caching feature
RST_OUT_CFG EXP_ADDR[15] Define Reset out pin behavior:
0: Reset out will deassert when SW writes to
CP_CNTL_STS register bit
1: Reset out will deassert when IA is out of reset
AVCAP Enable EXP_DB[0] Selects whether or not to mux AVCAP pins onto EXP, I2S,
and SC1 pins (B-step only):
0: Normal EXP, I2S, and SC1 bus operation (default)
1: AVCAP pins muxed onto EXP, I2S, and SC1 pins
These pins are normally outputs during functional mode, but implemented as bidirectional
I/O buffers. While RESET_INB is asserted, the outputs are forced tristate. EXP_ADDR pins
have a weak internal pull-up buffer, which will provide a default value of logic ‘1’ for all
functional straps. All other strap pins have a weak internal pull-down buffer which will
provide a default value of logic ‘0’. A strong external pull-up or pull-down resistor must be
present in order to override internal defaults.
All strap values are latched internally using the rising edge of SYS_PWR_GOOD, and then
distributed to the internal logic.