Specifications

Ref# 420826 Intel

Atom™ processor CE4100 35

Platform Design Guide

Intel Confidential

4.5.1.2 Cold Reset Sequence

PS_ON_PIC (PIC)

3.3V stand-by

Cold Reset

RESET_INB (PIC)

RSTRDYB (SOC)

SLPMODE (SOC)

SLPRDYB (SOC)

RSMRST# (PIC)

RSTWARN (PIC)

1 ms

3 to 5 sec

S5 to S0 Sequence Start

Not Valid

S5 to S0 Sequence Start

NOTE: External µController (EC) is always powered on

VDD

CK505 Clock

Clocks Valid

S0 to S5 Sequence Start

RB11

RB12

RB9

RB7

RB10

RB8

RB13

CoreVR_EN (PIC)

RA8, RA10

1. De-assert SYS_PWR_GOOD

2. De-assert PS_ON_PIC

3. Reset the rest of PIC signal in any order to prepare

for the next power on

SysVR_EN (PIC)

RA7, RA9

SYS_PWR_GOOD (PIC)

RC1

CLOCK_EN (PIC)

RB6

>2 ms