Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 3
Platform Design Guide
Intel Confidential
Contents
1 Introduction..............................................................................11
1.1 Related Documents .................................................................................12
1.2 Acronyms and Terminology ......................................................................15
2 Platform Overview ....................................................................19
3 Platform Stack-up and General Design Considerations..............21
3.1 Recommended Board Stack-up .................................................................22
3.1.1 1080 Prepreg .............................................................................25
3.1.2 PCB Technology Considerations ....................................................25
3.1.3 Multiple Impedance Target Considerations......................................26
3.1.4 Break Out Traces........................................................................26
4 Platform Power Distribution Guidelines ....................................27
4.1 Platform Power Rails................................................................................27
4.2 General Power Rail Design Guidelines .............................................................28
4.3 Power Decoupling ...................................................................................29
4.4 Power Sequence .....................................................................................31
4.4.1 Power-On Sequence Example .......................................................32
4.5 Reset Sequence ......................................................................................33
4.5.1 Reset Sequence Examples............................................................34
4.6 Straps ...................................................................................................37
4.7 Expansion Bus Strapping Design Topology ..................................................39
4.7.1 Design Example One ...................................................................39
4.7.2 Design Example Two ...................................................................40
4.8 Debug Port Guidelines .............................................................................41
5 System Memory Design Guidelines............................................42
5.1 Supported Configurations.........................................................................42
5.2 DDR2/DDR3 Pin Descriptions ....................................................................43
5.3 Decoupling Recommendations ..................................................................43
5.4 Package Length Compensation..................................................................44
5.5 DDR3 Design Topologies and Routing Guidelines .........................................46
5.5.1 DDR3 Guidelines for x16 Devices ..................................................46
5.5.2 DDR3 Guidelines for x8 Devices ....................................................50
5.6 DDR2 Design Topology and Routing Guidelines............................................55
5.6.1 DDR2 Guidelines for x16 Devices ..................................................55
5.6.2 DDR2 Guidelines for x8 Devices ....................................................60
5.7 VREF Circuit ...........................................................................................65
5.8 Miscellaneous Signals Design Guidelines.....................................................66
6 Video Output I
nterfaces............................................................67
6.1 Video DAC Interface ................................................................................67
6.1.1 Video DAC Application Model Examples ..........................................68