Specifications

28 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
4.2 General Power Rail Design Guidelines
• Place edge decoupling capacitors on bottom layer underneath the processor package
shadow, if there is not enough space on top layer
• Use the bulk and decoupling capacitors close to voltage regulator or power supply
module where the power is originated.
• Use sufficient Vias for connecting Power planes to carry the required current and with
inductance low enough to mitigate high di/dt currents impact.
• Use stitching capacitors wherever critical signals reference plane is changed.
• Use short and wide traces with at least two vias for connecting Bulk capacitors to power
and ground planes respectively.
• Check the Layout placement for components and Vias to ensure that copper area is not
degraded by overlapping of anti-pads, to avoid the return path and current capacity
issues.
• Reduce the inductance of Decoupling capacitors by reducing the distance from the pads
to the plane vias. Additionally use short, wide trace from Outer power VCC/VSS balls to
reduce the loop inductance.
• Use enough Decoupling capacitors for Termination power supplies close to Resistors /
Resistor Packs.
• In case of forced routing over the split plane (not recommended), use enough stitching
capacitor over the gap to mitigate the impedance discontinuity.