Specifications

26 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
3.1.3 Multiple Impedance Target Considerations
This platform will include various single-ended and differential impedance targets for the
various bus interfaces. Traditional methods of PCB impedance control focused on one,
single-ended target such as “4-mil line equals 55 Ω ±10%,” but there are multiple, single-
ended and differential impedance targets for this platform.
Table 3-1. 4-layer Board Impedance Target Example
Table 3-2. Additional Impedance Requirements Example
Target
Impedance
Tolerance
Trace
Width (in
mils)
Differential
Spacing (in
mils)
Notes
100 Ω, Differential
± 10%,
Reference Only
4 7
Fab vendor to provide detailed info. This
impedance is required for both outer
layers and inner layers.
90 Ω, Differential
± 10%,
Reference Only
4 4
Fab vendor to provide detailed info. This
impedance is required for both outer
layers and inner layers.
55 Ω, Single-ended
± 10%,
Reference Only
4 NA
Fab vendor to provide detailed info. This
impedance is required for both outer
layers and inner layers.
50 Ω, Single-ended
± 10%,
Reference Only
5 NA
Fab vendor to provide detailed info. This
impedance is required for both outer
layers and inner layers.
37.5 Ω, Single-ended
± 10%,
Reference Only
8 NA
Fab vendor to provide detailed info. This
impedance is required for both outer
layers and inner layers.
3.1.4 Break Out Traces
In order to breakout all signals on the Intel
®
Atom™ processor CE4100 in a 6-layer or 4-
layer board, “break out” traces are used in the BGA section. The use of break out traces
allows for tighter signal-to-via spacing for brief periods when normal spacing requirements
aren’t possible. In the BGA region of the Intel
®
Atom™ processor CE4100, trace-to-trace or
trace-to-via spacing can be 4 mils minimum.