Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 25
Platform Design Guide
Intel Confidential
3.1.1 1080 Prepreg
To achieve the stack-up described in the previous section, it is recommended that board
designers work closely with their PCB vendor in order to get the best combination of
material/thickness. PCB vendors use a 1080 prepreg material as opposed to 2116. A PCB
stack-up that uses 1080 prepreg allows for a decreased signal-to-reference plane height,
resulting in reduced cross-talk on high speed buses. This stack-up also allows for lower
trace impedances and lower Er which helps improve flight and rise times. With a stack-up
that uses 1080 prepreg material, substitute board designers are able to achieve the same
impedance targets with smaller trace widths when compared to a stack-up using 2116
prepreg. For example, a 5-mil line width on a stack-up that uses 2116 prepreg results in a
60 Ω nominal trace impedance, and a 4-mil line width on a stack-up that uses 1080 prepreg
results in a 50 Ω nominal trace impedance.
Board designers should pay close attention to the core material thickness used to ensure
the overall board thickness meets design for manufacturing specifications.
3.1.2 PCB Technology Considerations
The simulations and reference platform discussed in this design guide are based on the
following technology, and Intel recommends that designers adhere to these guidelines for a
platform based on the Intel
®
Atom™ processor CE4100 CRB.
It is important to note that variations in the stack-up of a board, such as changes in the
dielectric height, trace widths, and spacing, can impact the impedance, loss, and jitter
characteristics of all the interfaces. Such changes may be intentional, or the result of
variations encountered during the PCB manufacturing process. In either case, they must be
properly considered when designing interconnects.
The nominal stack-up in Figure 3-1 and Figure 3-2 assumes an overall board thickness of
0.057 inche
s or so. The figure also lists trends in manufacturing variances. Use these as a
guideline. Key aspects of the stack-up are as follows:
• Components are typically limited to single-sided placement on the top layer due to
increased manufacturing costs associated with double-sided placement.
• Microstrip traces on top-layer and bottom-layer are subject to solder mask and plating
impacts, which can affect impedance targets.
• Current High Volume Manufacturing (HVM) technology can support 4-mil minimum trace
width and 5-mil trace spacing dimensions between traces.
Note
Specific trace width and spacing targets for various interconnects can be found later in
this document in their respective chapters, as they reach a compromise between
impedance target, loss impacts, crosstalk immunity, and routing flexibility.