Specifications

24 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
Figure 3-2. Recommended 4-layer PCB Stack-up Dimensions
Notes
• Signal-end impedance target 37.5 Ω +/- 10% micro-strip routing for VDAC channel.
• Signal-end impedance target 55 Ω +/- 10% micro-strip routing for other than VDAC single-end channels.
• Differential impedance targets 90 Ω +/- 10% micro-strip routing for USBp/n differential channel.
• Differential impedance targets 100 Ω +/- 10% micro-strip routing for other differential channel other than
USBp/n differential channel.
• The typical trace width could be shrunk down from 4 mil to 3.5 mil for nominal 55-Ω single-end trace by
using different stack up, if the PCB manufacturing cost is not a concern.
• Different PCB vendors will have slightly different stack-up, as soon as the impedance of the trace width
with not larger than 4 mils width can meet nominal 55-Ω single-end impedance.
• This stack up is for reference only, particularly for DDRx16 configure.