Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 23
Platform Design Guide
Intel Confidential
Figure 3-1. Recommended 6-layer PCB Stack-up Dimensions
Notes
• Signal-end impedance target 37.5 Ω +/- 10% micro-strip routing for VDAC channel.
• Signal-end impedance target 55 Ω +/- 10% micro-strip routing for other than VDAC single-end channels.
• Differential impedance targets 90 Ω +/- 10% micro-strip routing for USBp/n.
• Differential impedance targets 100 Ω +/- 10% micro-strip routing for other differential channel other than
USBp/n differential channel.
• The typical trace width could be shrunk down from 4 mil to 3.5 mil for nominal 55-Ω single-end trace by
using different stack up, if the PCB manufacturing cost is not a concern.
• 2nd Reference is pretty weak for impedance controlled, i.e. the tracing routing on layer 3 with the 2nd
reference to Layer 4, or tracing routing on layer 4 with the 2nd reference to Layer 3, is pretty weak due
to the about 30 mils thick core.
• Different PCB vendors will have slightly different stack-up, as soon as the impedance of the trace, within
4 mils trace width, can meet nominal 55-Ω single-end impedance.
• This stack up is for reference only, particularly for DDRx8 configure.