Specifications

22 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
Note
The guidelines recommended in this document are based on Intel
®
Atom™ processor
CE4100 board development.
3.1 Recommended Board Stack-up
The recommended board stack-up for the Intel
®
Atom™ processor CE4100 platform is a
board stack-up yielding a target impedance of 55 Ω ± 10% for most single-end traces, with
a nominal 4-mil trace width. The intra-pair space of a differential pair channel will be
worked out respectively according to its targeted differential impedance, either 100 Ω or 90
Ω nominally.
Figure 3-1 and Figure 3-2 illustrate the typical dimensions of the metal and dielectric
materi
al thickness as well as the drawn trace width dimensions prior to lamination,
conductor plating, and etching. After the main board materials are laminated, conductors
plated, and etched, some dimensions will result in somewhat different values. As dielectric
materials become thinner, under/over etching of conductors alters their trace width, and
conductor plating makes them thicker. It is important to note that, for extracting electrical
models from transmission line properties, the final dimensions of signals after lamination,
plating, and etching should be used.
Figure 3-1 demonstrates the stack-up of a 6-
layer board, which is recommended for a
platform with 8 bits data width DDR2/3 memory device.
Figure 3-2 demonstrates the stack-up for a 4-
layer board, which is recommended for a
platform with 16 bits data width DDR2/3 memory device.
For the Intel
®
Atom™ processor CE4100 platform to meet the targeted nominal impedance
as the first priority, all the stack-ups, which are able to result in the same as, or smaller
than the recommended nominal trace width, are acceptable, when the manufacturing
process permits and the cost is not a concern.
With a particular stack up, assuming less than 4 mil trace width is used for nominal 55 Ω
single-end trace, the trace with for nominal 37.5 Ω will alter according, as well as the
minimum spacing requirement among all edges of single-end trace, differential pair traces
and poured ground patches. It might require further detailed SI analysis to address the
particular dimensions of both trace width and spacing.