Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 21
Platform Design Guide
Intel Confidential
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This section documents the Intel
®
Atom™ processor CE4100 board general layout and
routing guidelines. It does not discuss the functional aspects of any bus, or the layout
guidelines for an add-in device.
Note
If the guidelines listed in this document are not followed, thorough signal integrity and
timing simulations should be completed for each design. Even when the guidelines are
followed, Intel recommends that critical signals be simulated to ensure proper signal
integrity and flight time. Any deviation from the guidelines should be simulated.
The trace impedance typically noted (for example, 55 Ω ± 10%) is the “nominal” impedance
for a recommended nominal trace width (for example, 4-mil). It is based on the nominal
stack-up, similar to that shown in either Figure 3-1 (6-layer), or Figure 3-2 (4-layer), with
su
fficient spacing from either edge to the edge of the neighboring trace or poured ground
patch.
The rule of thumb for the spacing from the edge of one signal trace to the closest edge of
the neighboring trace or poured ground patch is at least 2.5 times of the nominal trace
width with the mostly used typical single-ended impedance. For differential pair channel, the
inter-pair space is generally at least 3 times the intra-pair space. In this case, the intra-pair
space is defined as the space between the two inner edges of the two involved traces in a
different pair, while the inter-pair is defined as the space from the outer edge in one
differential pair to the closest outer edge of the neighboring differential pair. The space from
the outer edge of one differential pair to the closet edge of any other signal trace or poured
round patch should not be less than the inter-pair space as well.
To meet the targeted nominal impedance as the first priority, all stack-ups, which result in
the same as (or smaller than) the nominal trace width are acceptable, as soon as the
manufacturing process permits and the cost is not a concern.
Note the trace impedance target assumes that the trace is not subjected to the EM fields
created by changing current in neighboring traces. It is important to consider the minimum
and maximum impedance of a trace based on the switching of neighboring traces when
calculating flight times.
Coupling between two traces is a function of the coupled length, the distance separating the
traces, the signal edge rate, and the degree of mutual capacitance and inductance. Using
wider spaces between the traces can minimize trace-to-trace coupling. In addition, wider
spaces reduce settling time. In order to minimize the effects of trace-to-trace coupling, the
routing guidelines documented in this section should be followed.