Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 135
Platform Design Guide
Intel Confidential
10.1.2.2 Audio and VDC Clock Input Design Example
The HDMI, VDC_CLK2, CLK27M and Audio reference clocks generate from IDT6V49061.
Only the HDMI Clock is differential signal. Others are single-ended signals .The diagram
below shows the IDT6V49061 HDMI Clock to the Intel
®
Atom™ processor CE4100 clock
channel Topology.
Figure 10-5. IDT6V49061 Audio and VDC CLK Topology
IDT6V49601 TL1 TL2 via TL3 Sodaville IDT6V49601 TL1 TL2 via TL3 Sodaville
Table 10-3. IDT6V49061 Clock Routing Guidelines
Parameters Routing Guidelines
Signal Group AUDIO_CLK and VDC_CLK
Reference Plane
Solid Ground Referenced.
Accompanying GND via is required for each signal net, if signal net layer transition
is not avoidable.
Layer Assignment MicroStrip (Top or Bottom layer)
Trace Impedance (Z0) 55 Ω +/-10% (Single-ended)
Parallel Terminal Rt 55 Ω +/-5%
Serial Terminal Rs 33 Ω +/-5%
Nominal Trace width 4.0 mils (single) & 4.0x7.0 (Diff.)
Nominal Trace Spacing
Intra-pair Trace Spacing: 7.0 mil
Inter-pair spacing (minimum): 21mils
To Other signal (minimum): 21 mils
(28 mils, if other signal is > 600MHz)
Nominal Trace Length
Keep all lengths as short as possible.
TL0: maximum 0.2”; TL1: maximum 0.5”;
TL2: maximum 0.2”; TL3: maximum 5.5”.
Length Matching requirements
Length matching from pin to pin,
or within the differential segment is within +/-50 mils.
Breakout
Minimize Lead-in into the Intel
®
Atom™ processor CE4100:
0.1” to 0.5” included in TL3
Inter-pair space >15 mils
Vias number Maximum 4 vias from IDT6V49061 to the Intel
®
Atom™ processor CE4100