Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 133
Platform Design Guide
Intel Confidential
Table 10-1. CK505 Clock Routing Guidelines
Parameters Routing Guidelines
Signal Group HPLL_REF_CLKP/N, SATA_CLKP/N, USB_CLKP/N
Reference Plane
Solid Ground Referenced. Accompanying GND via is required for each signal net, if
signal net layer transition is not avoidable.
Layer Assignment MicroStrip (Top or Bottom layer)
Trace Impedance (Z0)
100 Ω +/-10% (Differential)
Serial Terminal Rs 33 Ω +/-5%
Nominal Trace width 4.0 mils (single) & 4.0x7.0 (Diff.)
Nominal Trace Spacing
Intra-pair Trace Spacing: 7.0 mil
Inter-pair spacing (minimum): 21mils
To Other signal (minimum): 21 mils
(28 mils, if other signal is > 600MHz)
Nominal Trace Length
Keep all lengths as short as possible.
TL1: maximum 0.5”
TL1+TL2+TL3: maximum 6.0”
Length Matching requirements
Length matching from pin to pin, or within the differential segment is within +/-50
mils.
Breakout
Minimize Breakout into the Intel
®
Atom™ processor CE4100:
0.1” to 0.5” included in TL3
Inter-pair space >15 mils
Vias number Maximum 4 vias from CK505 (IDT) to the Intel
®
Atom™ processor CE4100
10.1.2 1IDT6V49061 Clock Topology
The HDMI, VDC_CLK2, CLK27M and Audio reference clocks generate from IDT6V49061.
Only the HDMI Clock is differential signal. Others are single-ended signals.
10.1.2.1 HDMI Clock Input Design Example
The diagram below shows the IDT6V49061 HDMI Clock to the Intel
®
Atom™ processor
CE4100 clock channel Topology.