Specifications

132 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
10.1 Reference Clock Routing
Guidelines
10.1.1 CK505 Clock Topology
The HPLL, SATA, and USB reference clocks generate from CK505. The diagram below shows
the CK505 to the Intel
®
Atom™ processor CE4100 clock channel Topology.
CK505 Clock Routing Guideline
The HDMI, VDC_CLK2, CLK27M and Audio reference clocks generate from IDT6V49061.
Only the HDMI Clock is differential signal. Others are single-ended signals .The diagram
below shows the IDT6V49061 HDMI Clock to the Intel
®
Atom™ processor CE4100 clock
channel Topology.
Figure 10-3. CK505 Reference Clock Topology
Notes:
• At least 3 times of inter-pair space to the other signals to mitigate Xtalk.
• Trace length skew in the differential pair is within 50mils.
CK505 TL1 TL2 via TL3 Sodaville
RS=33+/-5%