Specifications

128 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
9.2 HDVCAP Routing Topology
9.2.1 HDVCAP Design Topology 1
Figure 9-2. HDVCAP Signal Topology With NOR Boot
33
TL1
Break Out
Sodaville
TL2
TL3
TL6
MUX
TL4
TL5
NOR FLASH
Strap SW
TL7
HDMI RX
Table 9-2. HDVCAP Signal Length Table
Traces Description Layer
Min
Length
Max
Length
Trace
Width Spacing
TL1 SDV Breakout Micro strip 0.3” 0.7” 4 Mils >=4 Mils
TL2 Lead-in Micro strip 2.5” 4” 4 Mils >=8Mils
TL3 Lead-in Micro strip 0.1” 1.5” 4 Mils >=8Mils
TL4 Lead-in Micro strip 0.1” 1.0” 4 Mils >=8Mils
TL5 Lead-in Micro strip 0.1” 1.0” 4 Mils >=8Mils
TL6 Lead-in Micro strip 0.1” 1.5” 4 Mils >=8Mils
TL7 Lead-in Micro strip 0.1” 0.75” 4 Mils >=8Mils
Notes:
• Length matching between TL3+TL4 and TL6+TL7, within 0.25”.
• All trace impedance required to be 55Ω +/- 10%.
• All signals should be referenced to ground. Reference to unbroken power plane is also
accepted.