Specifications

122 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
8.9.3 SPI_MOSI and SPI_SCK Routing
Recommendation
Figure 8-26. SPI_MOSI and SPI_SCK signal Topology
Load 1 Load 2 Load 3
1K
Load 1 Load 2 Load 3
1K
Load 1 Load 2 Load 3
1K
Table 8-18. SPI_MOSI and SPI_SCK signal Topology list
Traces Layer Min Length
Max
Length
Trace:
Width/Spacing
Spacing from other
signals
w_TL0
Breakout
0.1” 0.5” 4 mils >=4 mils
w_TL1+w_TL2
Micro strip
0.1” 9” 4 mils >=8 mils
w_TL3/4/5
Micro strip
0.1” 6.0” 4 mils >=8 mils
Notes:
• All traces impedance required to be 55 Ω+/- 10%.
• All signals should be referenced to ground. Reference to unbroken power plane is also accepted.
• Rpu is 1KΩ with 5% variation.