Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 121
Platform Design Guide
Intel Confidential
8.9.2 SPI_MISO Routing Recommendation
Figure 8-25. SPI SPI_MISO signal Topology
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Table 8-17. SPI SPI_MISO signal Topology list
Traces Layer Min Length
Max
Length
Trace:
Width/Spacing
Spacing from other
signals
w_TL0
Breakout
0.1” 0.5” 4 mils >=4 mils
w_TL1
Micro strip
0.5” 10.0” 4 mils >=8 mils
w_TL2
Micro strip
0.5” 5.0” 4 mils >=8 mils
w_TL3/4
Micro strip
0.5” 5.0” 4 mils >=8 mils
Notes:
• All traces impedance required to be 55 Ω+/- 10%.
• w_TL2+w_TL3 is shorter than w_TL1 in the routing.
• All signals should be referenced to ground. Reference to unbroken power plane is also accept.