Specifications

120 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
8.9 SPI Serial Interface
The SPI serial interface on the Intel
®
Atom™ processor CE4100V provides two-channel (two
chip selects), 3wire serial input/output interface to connect to SPI-compatible devices
directly, such as audio DACs and frequency synthesizers in television tuners.
The SPI interface can support up to 16 bits. The 4-bit data size register (DSS) is used to
select the size of the data transmitted and received by the Synchronous Serial Port (SSP).
The data can be set from 4 bits to 16 bits. The FIFO is used to transfer serial data between
the system and an external peripheral. The FIFO buffer is four words deep by 16 bits wide.
The host CPU can load up to four 16-bit words, then it has to wait for the FIFO to empty to
reload.
The data frame may contain from 4 bits to 16 bits based on SPI_SSCR0 setting. The baud
rate is from 7.2Kbps to 1.8432Mbps.
8.9.1 SPI Serial Interface
Table 8-16. SPI Serial Interface Interconnects
Signal Description
SPI_MOSI
SPI DATA OUT: Output levels are 3.3 V CMOS
compatible; input is 5V tolerant.
SPI_MISO
SPI DATA INPUT: Output levels are 3.3 V CMOS
compatible; input is 5V tolerant.
SPI_SS[3:0]
SPI SELECT SIGNAL: When asserted low, the SPI
peripheral is selected. Four SPI devices can be
connected.
SPI_SCK SPI CLOCK OUPUT: Serial Clock accompanying data
Note: SPI pins can be left unconnected if not used.