Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 119
Platform Design Guide
Intel Confidential
Figure 8-24. GPIO Interface Topology
Table 8-15. GPIO Interface list
Traces Layer Min Length
Max
Length
Trace:
Width/Spacing
Spacing from other
signals
w_TL0
Breakout
0.1” 0.5” 4 mils >=4 mils
w_TL1+w_TL2
Micro strip
1” 15” 4 mils >=8 mils
Notes:
• Match W_TL1 within 0.25 inch.
• All traces impedance required to be 55 Ω+/- 10%.
• Simulation data based on IBIS model.
• All signals should be referenced to ground. Reference to unbroken power plane is also accepted.