Specifications

118 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
8.8 GPIO Interface
The General Purpose I/O interface provides additional flexibility to system designers.
GPIO[4:0] and GP_9 are dedicated GPIO pins and are not multiplexed with any other
function. The remaining GPIO pins are multiplexed with various functions. The MUX
function is controlled by the GPIO_MUXCNTL register in this unit.
SC0_VEN_GP_5
SC0_VSEL_GP_6
SC0_INS_GP_7
GBE_LINK_GP_8
UART0_DSRB_GPA_0
UART0_DTRB_GPA_1
UART0_DCDB_GPA_2
UART0_RIB_GPA_3
UART0_RTSB_GPA_4
UART0_CTSB_GPA_5
UART1_TXD_GPA_6
UART1_RXD_GPA_7
SC1_RST_GPA_8
DVSD2/SC1_VEN_GPA_9
SC1_VSEL_GPA_10
SC1_INS_GPA_11
All pins default to GPIO upon power up.
Note: GPIO signals GPA(11:8) can not be used as GPIOs when the AVCAP mode is enabled
by the AVCAP enable strap.
AVCAP Enable EXP_DB[0] Selects whether or not to mux AVCAP pins onto EXP, I2S,
and SC1 pins (B-step only):
0: Normal EXP, I2S and SC1 bus operation (default)
1: AVCAP pins muxed onto EXP, I2S, and SC1 pins