Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 117
Platform Design Guide
Intel Confidential
8.7.2 UART0_DSRB Signal Recommendation
Figure 8-23. UART0_DSRB signal Topology
Table 8-14. UART0_DSRB signal Topology
Traces Layer Min Length
Max
Length
Trace:
Width/Spacing
Spacing from other
signals
w_TL0
Breakout
0.1” 0.5” 4 mils >=4 mils
w_TL1+w_TL2
Micro strip
0.5” 20” 4 mils >=8 mils
Notes:
• All traces impedance required to be 55 Ω +/- 10%.
• Simulation data based on Cin=10pF (no IBIS models).
• All signals should be referenced to ground. Reference to unbroken power plane is also accepted.