Specifications

114 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
8.6 I
2
C* Interface
The I
2
C Bus Interface Unit allows the Intel
®
Atom™ processor CE4100 to serve as a master
device residing on the I
2
C bus. The I
2
C bus is a serial bus developed by Philips Corporation
consisting of a two-pin interface.
Note
Please also refer to www.semiconductors.philips.com
for detail I
2
C electrical design
guide.
The I
2
C bus allows the Intel
®
Atom™ processor CE4100 to interface to other I
2
C peripherals
and microcontrollers for system management functions. Serial Data/Address (SDA) is the
data pin for input and output functions and Serial Clock Line (SCL) is the clock pin for
reference and control of the I
2
C bus.
Figure 8-21. I2C Bus Interconnects Topology
Table 8-12. I2C interconnection list
Traces Layer Min Length
Max
Length
Trace:
Width/Spacing
Spacing from other
signals
w_TL0
Breakout
0.1” 0.5” 4 mils >=4 mils
w_TL1+w_TL2
Micro strip
0.1” 4” 4 mils >=8 mils
w_TL3
Micro strip
0” 1.0” 4 mils >=8 mils
w_TL4
Micro strip
0.1” 5” 4 mils >=8 mils
Notes:
• The signal group is shown for SDA and SCL.
• All traces impedance required to be 55 Ω +/- 10%.
• Pull-up resistors is 2.2KΩ for I2C bus with 5% variation.
• Simulation data based on Cin=10pF (no IBIS models).
• All signals should be referenced to ground. Reference to unbroken power plane is also accepted.