Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 113
Platform Design Guide
Intel Confidential
8.5.7 NAND_CLK_X_OUT/IN Topology
Traces Layer Param
Min
Length
Max
Length
Trace:
Width/Spacing
Spacing from
other signals
Notes
w_TL0
Breakout Len0
0.1” 0.5” 4 mils >=4 mils
1, 2, 3
w_TL1
Micro
strip
Len1
0.5” 4.5” 4 mils >=10 mils
1, 2, 3
w_TL2
Micro
strip
Len2
0.5” 5” 4 mils >=10mils
1, 2, 3
Notes:
• All trace impedance required to be 55Ω +/- 10%.
• All signals should be referenced to ground. Reference to unbroken power plane is also accepted.
• Total trace length of NAND_CLK_X_OUT/IN should be twice of the trace length of NAND_IO signals.
Note: Intel maintains a list of NAND parts that pass the Intel boot sequence validation
testing as a reference for the designer. If the designer prefers to choose a NAND part not
included in the list, be aware that the part could potentially fail Intel validation testing.
Please check with Intel FAE (Field Application Engineer) for special NAND vendor parts. For
a list of validated NAND parts, refer to the Intel
®
Atom™ processor CE4100 Sighting/Errata
Report and Specification Update (Reference Number: 426684).