Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 105
Platform Design Guide
Intel Confidential
8.4.2 Expansion Bus Address, EXP_ALE and
EXP_IO_WRB
The address bus is multiplexed. Address bus bits [15:0] are dedicated; address bits [23:15]
are multiplexed onto EXP_DATA_A[7:0] and must be captured using an external address
latch controlled by EXP_ALE; address bits [25] and [24] are multiplexed onto EXP_IO_WRB
and EXP_IO_RDB, respectively, and must also be latched externally.
Figure 8-17 shows the topology for the Address bus.
Figu
re 8-17. Expansion Bus Address ADDR<0, 2-15>, EXP_ALE and EXP_IO_WRB
Topology
Table 8-9. Expansion Address/Data Bus Star Topology
Traces Layer Min Length
Max
Length
Trace:
Width/Spacing
Spacing from other
signals
w_TL0
Breakout
0.1” 0.5” 4 mils >=4 mils
w_TL1+w_TL2
Micro strip
0.1” 7” 4 mils >=8 mils
w_TL3/4
Micro strip
0 2 4 mils >=8 mils
Notes:
• Topology signal names are: EXP_ADDR[0…15], EXP_IO_WRB and EXP_ALE
• Match all signals within 0.25 inch, besides match routing for EXP_ADDR[0…15] within 0.1”
• All trace impedance required to be 55 Ω +/- 10%.
• All signals should be referenced to ground. Reference to unbroken power plane is also accepted.