Specifications

104 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
8.4.1 Expansion Bus Chip Select
The Expansion Bus includes a 26-bit address bus and two 8-bit wide data paths. It maps
transfers between the internal Backbone bus and the external devices. The bus controller
has an address decoder that generates up to four device select strobes. The four devices
together take 256 MB of contiguous IA-32 address space. The start address of these blocks
is hard-coded on the 64-MB boundaries, and no other device may be inserted into the 64-
MB address space occupied by this EXP_CSnB.
The typical application of the chip can have the following EXP_CSnB pin connections for the
signals EXP_CS[3:0]B.
• EXP_CS0B - Boot Flash Memory device
• EXP_CS1B - Second Flash Memory device, front panel interface, miscellaneous interface
devices
The Intel
®
Atom™ processor CE4100 always boots from the Expansion Bus. The EXP_CS0B
output is predefined to drive a NOR flash memory chip that is used for bootstrapping. The
boot flash must be connected to EXP_CS0B. Additional flash memory devices may be
connected to EXP_CS1B, EXP_CS2B, and so on if greater storage capacity is needed.
Figure 8-16. Expansion Bus Topology for EXP_CS[3:0]B
Table 8-8. Expansion Bus Topology for EXP_CS[3:0]B
Traces Layer Min Length
Max
Length
Trace:
Width/Spacing
Spacing from other
signals
w_TL0
Breakout
0.1” 0.5” 4 mils >=4 mils
w_TL1+w_TL2
Micro strip
0.1” 8.5” 4 mils >=8 mils
Notes:
• Match all signals within 0.25”.
• All trace impedance required to be 55 Ω+/- 10%.
• All signals should be referenced to ground. Reference to unbroken power plane is also accepted.