Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 103
Platform Design Guide
Intel Confidential
8.4 Expansion Bus Interface
Guidelines
The expansion bus is a general-purpose synchronous bus that can host 16-bit and 8-bit
memory devices or peripherals such as NOR flash and other peripherals such as Cable Cards
and front panel controllers. The expansion bus includes a 26-bit address bus and two 8-bit
wide data paths. It maps transfers between the internal backbone bus and the external
devices. The bus controller has an address decoder, which generates up to four device
select strobes. The expansion bus also provides a fixed reference clock frequency of 62.5 or
66.6 MHz.
Figure 8-15. Expansion Bus Implementation Showing 26-bit Addressing Example
SAP-BI Gasket
Backbone
Scalable Agent Port (SAP)
AHB Bridge
AHB Bus
Expansion Bus InterfaceAPB Contoller
.
IORDB
RDB
WRB
EXP_CS0B
Internal
Peripherals
Flash Memory
Bank 0
Flash Memory
Bank 1
External Device 0 External Device 1
EXP_Data_A[7:0]
EXP_Data_B[7:0]
EXP_ADDR[15:0]
EXP_ADDR[25:16]
IOWRB
EXP_CS1B
EXP_CS2B
EXP_CS3B
CSB CSB CSB CSB
EXP_ALE
LATCH
The Expansion bus can support several different topologies. Topologies and specifics for
interfacing to peripherals are denoted in this section. It is recommended that simulations be
done for peripherals that may have differing characteristics not detailed in this platform
design guide.