Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 101
Platform Design Guide
Intel Confidential
Figure 8-12. GBE_TXCTL
Figure 8-13. GBE_REFCLK
Table 8-6. GBE Transmitter Routing Guidelines
Traces Description Layer
Min
Length
Max
Length
Trace
Width
Spacing Notes
TL1 SDV Breakout
Micro
strip
0.1” 0.5” 4 Mils >=4 Mils
TL2 Lead-in
Micro
strip
0.5” 6.5” 4 Mils >=10 Mils
TL3 breakin
Micro
strip 0.5” 1” 4 Mils >=4 Mils
Length
match ±0.25” TL1+TL2+TL3
Notes:
• GBE TX signal group: GBE_TXCLK, and GBE_TXDATA<0-3>. Match all signals with in +/- 0.25” respect to its
clock.
• All trace impedance required to be 55 Ω +/- 10%.
• Trace widths provided here are targeted only for 55 Ω.
• All signals should be referenced to ground. Reference to unbroken power plane is also accepted.
• No additional probe points to be used. Minimize the vias to be used.
• Spacing among GBE_TXCLK, GBE_REFCLK and GBE_RXCLK should be larger than 20 mils.