Intel® Atom™ processor CE4100 Platform Design Guide May 2010 Revision 1.
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Contents 1 Introduction ..............................................................................11 1.1 Related Documents .................................................................................12 1.2 Acronyms and Terminology ......................................................................15 2 Platform Overview ....................................................................19 3 Platform Stack-up and General Design Considerations..............21 3.
6.1.2 6.2 6.3 HDMI Transmitter Interface ......................................................................74 6.2.1 Detailed HDMI Routing Example....................................................75 6.2.2 HDMI ESD Protector Routing Suggestions.......................................77 Transport Stream Input Ports ...................................................................83 6.3.1 7 8 Video Calibration Circuit ..............................................................
9 High Definition Video Capture (HDVCAP) ................................126 9.1 HDVCAP Signals Interface ...................................................................... 126 9.2 HDVCAP Routing Topology...................................................................... 128 9.2.1 HDVCAP Design Topology 1........................................................ 128 9.2.2 HDVCAP Design Topology 2........................................................ 129 10 Platform Clock Design Guidelines ...
List of Tables Table 1-1. Related Documents ................................................................................................................... 12 Table 1-2. Acronyms and Terminology ....................................................................................................... 15 Table 3-1. 4-layer Board Impedance Target Example................................................................................ 26 Table 3-2. Additional Impedance Requirements Example.....................
Table 8-4. USB Channel Routing Guidelines.............................................................................................. 96 Table 8-5. USBRBIASP/ USBRBIASN Routing Guidelines........................................................................ 97 Table 8-6. GBE Transmitter Routing Guidelines....................................................................................... 101 Table 8-7. GBE RX Routing Guidelines..........................................................................
List of Figures Figure 2-1. Platform Overview .................................................................................................................... 20 Figure 3-1. Recommended 6-layer PCB Stack-up Dimensions.................................................................. 23 Figure 3-2. Recommended 4-layer PCB Stack-up Dimensions.................................................................. 24 Figure 4-1. Power on sequence...................................................................
Figure 8-7. USBRBIAS/USBRBIASN Connection ...................................................................................... 97 Figure 8-8. Design Example........................................................................................................................ 98 Figure 8-9. GBE Interface Clock Signal Design Example......................................................................... 100 Figure 8-10. GBE TX Interface (except GBE_TXCLK) ..................................................
Revision History Date Revision Reference # Description March, 2009 0.5 26337 Initial version. May, 2009 0.6 420826 De-classification from “Restricted Secret” to “Confidential”. June, 2009 0.8 420826 Update to B stepping. Added Video capture, clock design recommendation and checklist for schematic and layout etc. December, 2009 1.0 420826 Replaced codename “Sodaville” with official name “Intel® Atom™ processor CE4100”; Many additional changes throughout. May, 2010 1.
1 Introduction This Intel® Atom™ processor CE4100 Platform Design Guide (PDG) provides design recommendations for platform designs using the Intel® Atom™ processor CE4100. The Intel® Atom™ processor CE4100 Development Platform is a non-form-factor development board that may be used as a reference design.
1.1 Related Documents Table 1-1 provides a list of related documents. The titles listed are available to subscribed customers with a current CNDA in place and an Intel Business Link (IBL account). For account subscription and validation or restricted distribution documents, contact your local Intel field representative.
Intel® Atom™ processor CE4100 Documents Note: The following documents are contained within the Consumer Electronics: Intel® Atom™ processor CE4100 (formerly Sodaville) Collateral List, which is contained within the EDK listed in the note at the introduction to this section.
JEDEC DDR3 Specifications http://www.jedec.org Low Pin Count Interface Specification, Revision 1.1 (LPC) http://developer.intel.com/design/chipsets/industry/ lpc.htm System Management Bus Specification, Version 2.0 (SMBus) http://www.smbus.org/specs/ PCI Local Bus Specification, Revision 2.3 (PCI) http://www.pcisig.com/specifications Universal Serial Bus Revision 2.0 Specification (USB) http://www.usb.
1.2 Acronyms and Terminology Table 1-2. Acronyms and Terminology Acronym Definition ACP Analog Copy Protection (ACP) is a proprietary system developed and patented by Macrovision* AES Advanced Encryption Standard — a state of the art strong encryption algorithm (developed by Rijndael) and chosen by the United States National Institute of Standards and Technology on October 2, 2000.
Acronym Definition DVB Digital Video Broadcasting — a set of open worldwide standards that define digital broadcasting using existing satellite, cable, and terrestrial infrastructures. It uses the MPEG-2 specification as a universal foundation and expands it with DVB data structures and processes; DVB-compliant digital broadcasting and equipment is widely available to consumers and is indicated with the DVB logo.
Acronym Definition NIM Network Interface Module — integrated tuner and digital demodulator in (satellite) TV systems. The DVB NIMs output an MPEG transport stream. NOR A logical operator the consists of a logical OR followed by a logical NOT and returns a true value only if both operands are false. Used to describe a type of FLASH memory based upon NOR gates. NTSC National Television System Committee, established North American 525-line analog broadcast TV standard about 60 years ago.
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2 Platform Overview The Intel® Atom™ processor CE4100 is a System-On-Chip (SOC) intended for use in systems which bring network connectivity into the living room such as connected cable settop boxes, IP set-top boxes, blue-laser disk players/recorders (Blu-Ray), and so on. The Intel® Atom™ processor CE4100 supports processing of dual high-definition (HD) audio/video (AV) streams for local TV/display and serving of multiple AV streams for remote TVs.
Figure 2-1.
3 Platform Stack-up and General Design Considerations This section documents the Intel® Atom™ processor CE4100 board general layout and routing guidelines. It does not discuss the functional aspects of any bus, or the layout guidelines for an add-in device. Note If the guidelines listed in this document are not followed, thorough signal integrity and timing simulations should be completed for each design.
Note The guidelines recommended in this document are based on Intel® Atom™ processor CE4100 board development. 3.1 Recommended Board Stack-up The recommended board stack-up for the Intel® Atom™ processor CE4100 platform is a board stack-up yielding a target impedance of 55 Ω ± 10% for most single-end traces, with a nominal 4-mil trace width. The intra-pair space of a differential pair channel will be worked out respectively according to its targeted differential impedance, either 100 Ω or 90 Ω nominally.
Figure 3-1. Recommended 6-layer PCB Stack-up Dimensions Notes • • • • • • • • Signal-end impedance target 37.5 Ω +/- 10% micro-strip routing for VDAC channel. Signal-end impedance target 55 Ω +/- 10% micro-strip routing for other than VDAC single-end channels. Differential impedance targets 90 Ω +/- 10% micro-strip routing for USBp/n. Differential impedance targets 100 Ω +/- 10% micro-strip routing for other differential channel other than USBp/n differential channel.
Figure 3-2. Recommended 4-layer PCB Stack-up Dimensions Notes • • • • Signal-end impedance target 37.5 Ω +/- 10% micro-strip routing for VDAC channel. Signal-end impedance target 55 Ω +/- 10% micro-strip routing for other than VDAC single-end channels. Differential impedance targets 90 Ω +/- 10% micro-strip routing for USBp/n differential channel. Differential impedance targets 100 Ω +/- 10% micro-strip routing for other differential channel other than USBp/n differential channel.
3.1.1 1080 Prepreg To achieve the stack-up described in the previous section, it is recommended that board designers work closely with their PCB vendor in order to get the best combination of material/thickness. PCB vendors use a 1080 prepreg material as opposed to 2116. A PCB stack-up that uses 1080 prepreg allows for a decreased signal-to-reference plane height, resulting in reduced cross-talk on high speed buses.
3.1.3 Multiple Impedance Target Considerations This platform will include various single-ended and differential impedance targets for the various bus interfaces. Traditional methods of PCB impedance control focused on one, single-ended target such as “4-mil line equals 55 Ω ±10%,” but there are multiple, singleended and differential impedance targets for this platform. Table 3-1. 4-layer Board Impedance Target Example Table 3-2.
4 Platform Power Distribution Guidelines This chapter provides an example for board power delivery of an Intel® Atom™ processor CE4100-based platform. There are many power distribution methods that achieve similar results. It is critical to completely analyze the effects of any changes, and design accordingly if deviating from this example. 4.1 Platform Power Rails The Intel® Atom™ processor CE4100 requires up to 5 externally supplied voltages, 3.3V, 1.8V, and 1.5V, 1.05V and core power 0.95V – 1.05V.
4.2 • • • • • • • • • 28 General Power Rail Design Guidelines Place edge decoupling capacitors on bottom layer underneath the processor package shadow, if there is not enough space on top layer Use the bulk and decoupling capacitors close to voltage regulator or power supply module where the power is originated. Use sufficient Vias for connecting Power planes to carry the required current and with inductance low enough to mitigate high di/dt currents impact.
4.3 Power Decoupling Table 4-1. Decoupling Example Note: A “yes” in the “Isolation” column means that additional filtering may be required in some product configurations. Interface Voltage Isolation SC, SPI,UART, I2S, TS V3P3 No Size Voltage/ Type Value Qty 0.1uF 5 0402 16V/Y5V 1.0uF 3 0402 6.3V/Y5V 4.7uF 1 0603 10V/Y5V 120 0hmFB 1 2 120 0hmFB 1 2 0.1uF 1 0402 16V/Y5V 1.0uF 1 0402 6.3V/X5R 0.1uF 2 0402 16V/Y5V 1.0uF 2 0402 6.3V/Y5V 4.
Interface Voltage Isolation Value Qty Size Voltage/ Type NETs in Package 680uF 1 7343 4V/TANT 1000uF 1 RDL 330 Ω FB 1 22UF 1 0805 6.3V/X5R VCC1P8_DDR_CK CORE 0.1uF 3 0402 16V/Y5V VCC1P05_HPLL_CORE USB 560uF 4 RDL 4V/ALUM VCC1P05_USB_CORE HDMI_PLL 4.7uF 1 0603 16V/Y5V VCCA1P05_HDMI_PLL 0.1uF 2 0603 25V/Y5V VCCA1P05_HPLL IA 10uF 2 0805 6.3V/X5R VCC1P05_IA LCC 1.0uF 2 0402 6.3V/Y5V VCC1P05_LCC_PC6 FUSE 10uF 1 0805 120 Ω FB 1 120 Ω FB 1 10uF 2 0805 6.
4.4 Power Sequence From a power management point of view, the Intel® Atom™ processor CE4100 only supports on/off. There is no special power-sequencing requirement for the third party ICs used on the platform boards. However, the following two requirements for the Intel® Atom™ processor CE4100 need to be met at the board level. Power Supply Sequencing Rule 1 If USB 1.8V comes up prior to USB 3.3V supply, the 3.3V supply must trail within 0.7V of the 1.8V supply. The same 0.7V restriction applies if USB 3.
4.4.1 Power-On Sequence Example On the development platform, an external microcontroller (PIC24FJ64GA004) is used to control platform level power up/off sequence. Figure 4-1. Power on sequence S5 (Soft Off) to S0 (Full On) PWROK USB_ENB_PIC# (PIC) RA4 SYS_PWR_GD (PIC) RA1 RSTWARN (PIC) RB9 UART1_MC_RX (PIC) RB3 150 - 200ms 1 ms > 100us PS_ON_PIC (PIC) RB13 RESET_INB (PIC) RB12 PWR Button/IR/CEC Event >5 ms RSMRST# (PIC) RB11 SMI# (PIC) RB6 >5 ms 3.
4.5 Reset Sequence RESET_INB and SYS_PWR_GOOD signals are all 3.3V power well input signals and used to initiate a reset sequence for the Intel® Atom™ processor CE4100. The Intel® Atom™ processor CE4100 releases RESET_OUTB to show IA core is out of reset. PWROK signal is not used on the Intel® Atom™ processor CE4100. This signal can be connected to ground directly. RESET_INB RESET_INB is an active low chip reset signal. This signal must be driven to 3.3 V for a logic 1.
4.5.1 Reset Sequence Examples The section lists the warm reset, cold reset, and catastrophic shut down sequence diagrams. 4.5.1.
4.5.1.2 Cold Reset Sequence Cold Reset S0 to S5 Sequence Start 3.
4.5.1.3 Catastrophic Shutdown An internal shutdown would typically occur during a thermal catastrophic event. Note: On the Intel development board, there is a third party IC (PIC24) used for platform/system power management. Above power sequence/reset sequence examples are taken from the Intel Media Processor CE 3100 & Intel Atom processor CE4100 PIC Application Note (Ref #397803). Please refer to this document for more details.
4.6 Straps The following table lists all of the straps, grouped into two categories. • Miscellaneous Straps: The DDR_X8, I2C_LED and TRUST_BOOT straps both have a weak internal pull-down for a default value of ‘0’, and require a 1.0~1.1-KΩ pull-up to obtain the non-default value of ‘1’. • Expansion Bus Straps: The EXP_ADDR[15:0] straps each have a weak internal pull-up for a default value of ‘1’, and require a 4.
Strap Name Pin Name Description DDR_SPEED EXP_ADDR[8:6] Define DDR2/3 Frequency: 000: DDR3-800 Supported 001: DDR3-1066 Supported 010: DDR3-1333 Supported 011: Reserved 100: DDR2-800 Supported 101: Reserved 110: Reserved 111: Reserved BOOT_WIDTH EXP_ADDR[9] Defines width of flash 0: x8 flash 1: x16 flash NAND_BOOT EXP_ADDR[10] Enable boot from NAND flash 0: Normal operation 1: Boot from NAND flash NAND_NUM_ADDR_CYCLES EXP_ADDR[11] Determines whether NAND requires 4-cycle or 5-cycle addressing
4.7 Expansion Bus Strapping Design Topology The Expansion bus interface needs to be designed for strapping purposes at the beginning of system power up. During system power up, this interface can be used as a communication interface between the SOC and NOR flash or between the SOC and high definition video capture. 4.7.1 Design Example One • • NOR or other devices CE4100 PKG This design topology is used on the Intel innovation model reference design board.
4.7.2 Design Example Two This design topology is used on Intel development platform. • 40 Since the Intel development platform is for debugging and validation, the switch chip is added and the switch is available on board for turning on/off to achieve pull down/pull up.
4.8 Debug Port Guidelines Please refer to the latest revision of the Debug Port Design Guide –External Version (document #374175) for details on the implementation of the debug port. Intel recommends implementing this port on all development platforms design, if at all possible, since it greatly speeds up the initial board power-on and debug processes. For debugger tool information and support, please visit www.arium.com.
5 System Memory Design Guidelines The Intel® Atom™ processor CE4100 supports two DDR2/DDR3 SDRAM channels supporting up to 1GB memory per channel. The design will support 512-Mb, 1-Gb or 2-Gb devices in a single rank configuration. In support of the design guide, one channel may support one device density and the other channel may support another configuration.
5.2 DDR2/DDR3 Pin Descriptions Table 5-3 provides a summary of the signal pins specified by the DDR2/DDR3 protocol. For detailed description of pins and DDR2/DDR3 protocol, refer to the JESD79-2/3 DDR2/DDR3 SDRAM specification. Table 5-3.
5.4 Package Length Compensation Package length compensation is required for DDR3 based platform DDR section length match. Package length information is shown in Table 5-4. Table 5-4. Memory Interface Package Lengths Channel A Signal Name Channel B Package Length (mils) Signal Name Package Length (mils) DDRA_WEB 377.99 DDRB_WEB 456.84 DDRA_RASB 491.67 DDRB_RASB 464.11 DDRA_ODT 512.07 DDRB_ODT 521.56 DDRA_MA[9] 513.96 DDRB_MA[9] 439.88 DDRA_MA[8] 405.03 DDRB_MA[8] 490.
Channel A Signal Name Channel B Package Length (mils) Signal Name Package Length (mils) DDRA_DQ[3] 351.79 DDRB_DQ[3] 353.90 DDRA_DQ[29] 482.03 DDRB_DQ[29] 587.89 DDRA_DQ[28] 472.59 DDRB_DQ[28] 420.46 DDRA_DQ[27] 385.52 DDRB_DQ[27] 524.57 DDRA_DQ[26] 364.55 DDRB_DQ[26] 434.76 DDRA_DQ[25] 481.65 DDRB_DQ[25] 529.19 DDRA_DQ[24] 385.38 DDRB_DQ[24] 447.34 DDRA_DQ[23] 237.05 DDRB_DQ[23] 325.16 DDRA_DQ[22] 364.80 DDRB_DQ[22] 380.25 DDRA_DQ[21] 315.79 DDRB_DQ[21] 412.
5.5 DDR3 Design Topologies and Routing Guidelines 5.5.1 DDR3 Guidelines for x16 Devices 5.5.1.1 Clock Signals – CLK, CLK_B Table 5-5. Clock Signals – DDRA_CLK/CLKB, DDRB_CLK/CLKB Parameter Routing Guidelines Signal Group CLK Reference Plane Recommended Layer Route over unbroken power plane or ground plane Micro-strip Breakout Trace Width and spacing 4 mils x 3.
Table 5-6. DDR3 Memory Clock Topology Table Traces TL1 Description Breakout Layer Min Length Max Length Trace Width Spacing Micro strip 0.05" 0.5" 4 Mils 3.5 Mils TL2 Lead-in Micro strip 1" 2.5" 4 Mils 7 Mils TL3 Device 1 stub Micro strip 0.05" 0.25" 4 Mils 3.5 Mils TL4 T line Micro strip 0.05" 1" 4 Mils 7 Mils TL5 Device 2 stub Micro strip 0.05" 0.25" 4 Mils 3.5 Mils TL6 T line Micro strip 0.05" 1" 4 Mils 7 Mils 5.5.1.
The VREF, which is 1/2 of VCC1P5_DDR (VCC1P5_DDR for DDR2), termination stubs can be placed either on the stubs or on the fly traces. Termination packs should be either individual or X4 resistor packs. Resistor packs, like X8 or more, should not be used. Figure 5-2. DDR3 Address, Command and Control Topology with Two Loads Table 5-8. DDR3 Address, Command, and Control Topology Table Traces Description Layer Min Length Max Length Trace Width Spacing within Group TL1 Micro strip 0.05" 0.
5.5.1.3 Data and Data Strobe Signals – DQ/DM/DQS Table 5-9. Data and Strobe Signals – DQ/DM/DQS Parameter Routing Guidelines Signal Group Source Synchronous [ DQ/DM/DQS ] Reference Plane Micro-strip routing: Route over unbroken ground plane. Breakout width and spacing 4 mils width on 4mils spacing Trace Impedance 55 Ω +/- 10% Trace Spacing within byte lane (Edge to edge) 4 mils spacing in breakout regions. >16 mils. Between all DQ Signals. >20 mils.
Table 5-10. DDR3 DQ/DM/DQS Topology Table Traces Description TL1 Breakout Layer Min Length Max Length Trace Width Spacing Micro strip 0.05” 0.5” 4 Mils >=4 Mils Micro strip 1” 3.5” 4 Mils >=16 Mils TL2 Lead-in TL3 Memory Breakout Micro strip 0.05” 0.5” 4 Mils >=4 Mils TL4* LA Breakout 0” 0.1” 4 Mils >=16 Mils Micro strip 5.5.2 DDR3 Guidelines for x8 Devices 5.5.2.1 Clock Signals – CLK, CLKB Notes OPTIONAL* Table 5-11.
Table 5-12. DDR3 Memory Clock Topology Table Traces TL1 Description Breakout Layer Min Length Maximum Length Trace Width Spacing Micro strip 0.05" 0.5" 4 Mils >= 3.5 Mils Spacing to nearest signals TL2 Lead-in Micro strip 0.5" 1.8" 4 Mils >=7 Mils >= 20 mils TL3 Between Devices Micro strip 0.1" 0.8" 4 Mils >=7 Mils >= 20 mils TL4 Device Breakout Micro strip 0.05" 0.2" 4 Mils >= 3.
5.5.2.2 Address, Command and Control Table 5-13.
Table 5-14. DDR3 Address, Command, and Control Topology Table Traces Description TL1 Breakout Layer Min Length Maximum Length Trace Width Spacing Micro strip 0.05" 0.5" 4 Mils >=4 Mils TL2 Lead-in Micro strip 0.5" 1.3" 4 Mils >=10 Mils TL3 Breakout Micro strip 0.05" 0.5" 4 Mils >=4 Mils TL4 Between Devices Micro strip 0.1" 0.8" 4 Mils >=10 Mils TL5 Device Breakout Micro strip 0.05" 0.
5.5.2.3 Data and Data Strobe Signals – DQ/DM/DQS Table 5-15. Data and Strobe Signals – DQ/DM/DQS Parameter Routing Guidelines Signal Group DQ/DM/ DQS Reference Plane Recommended layer Route over unbroken ground plane. Micro-strip routing. Breakout width and spacing 4 mils width on 4mils spacing Trace Impedance 55 Ω +/- 10% Trace Spacing (Edge to edge) Within group (byte lane) >=16 mils for DDR3-1333.
5.6 DDR2 Design Topology and Routing Guidelines 5.6.1 DDR2 Guidelines for x16 Devices 5.6.1.1 Clock Signals – CLK, CLKB Table 5-17. Clock Signals – DDRA_CLK/CLKB, DDRB_CLK/CLKB Parameter Routing Guidelines Signal Group CLK Reference Plane Recommended Layer Route over unbroken power plane or ground plane Micro-strip Breakout Trace Width and spacing 4 mils x 3.
Table 5-18. DDR2 Memory Clock Topology Table Traces TL1 Description Min Length Max Length Trace Width Spacing Micro strip 0.05" 0.5" 4 Mils 3.5 Mils Lead-in Micro strip 1" 2.5" 4 Mils 7 Mils TL3 Device 1 stub Micro strip 0.05" 0.25" 4 Mils 3.5 Mils TL4 T line Micro strip 0.05" 1" 4 Mils 7 Mils TL5 Device 2 stub Micro strip 0.05" 0.25" 4 Mils 3.5 Mils TL6 T line Micro strip 0.05" 1" 4 Mils 7 Mils TL2 Breakout Layer 5.6.1.
Figure 5-8. DDR2 Address, Command and Control Topology with Two Loads Table 5-20. DDR2 Address, Command, and Control Topology Table Traces Description Layer Min Length MaxLength Trace Width Spacing TL1 Micro strip 0.05" 0.5" 4 Mils >=4 Mils Breakout TL2 Lead-in Micro strip 0.5" 2" 4 Mils >=10 Mils TL3 Breakout Micro strip 0.05" 0.5" 4 Mils >=4 Mils TL4 T branch Micro strip 0.1" 0.6" 4 Mils >=10 Mils TL5 Device Breakout Micro strip 0.05" 0.
5.6.1.3 Data and Data Strobe Signals – DQ/DM/DQS Table 5-21. Data and Strobe Signals – DQ/DM/DQS Parameter Routing Guidelines Signal Group Source Synchronous [ DQ/DM/ DQS ] Reference Plane Micro-strip routing: Route over unbroken ground plane Breakout width and spacing 4 mils width on 4mils spacing Trace Impedance 55 Ω +/- 10% Trace Spacing within byte lane (Edge to edge) 4 mils spacing in breakout regions >10 mils. Between all DQ Signals >20 mils.
Table 5-22. DDR2 DQ/DM/DQS Topology Table Traces Description TL1 Breakout Layer Min Length Max Length Trace Width Spacing Micro strip 0.05” 0.5” 4 Mils >=4 Mils Micro strip 1” 3.5” 4 Mils >=10 Mils TL2 Lead-in TL3 Memory Breakout Micro strip 0.05” 0.5” 4 Mils >=4 Mils TL4* LA Breakout 0” 0.
5.6.2 DDR2 Guidelines for x8 Devices 5.6.2.1 Clock Signals – CLK, CLKB Table 5-23. Clock Signals – DDRA_CLK/CLKB, DDRB_CLK/CLKB, Parameter Routing Guidelines Signal Group CLK Reference Plane Recommended Layer Route over unbroken power plane or ground plane Micro-strip Breakout Trace Width and spacing 4 mils x 3.
Table 5-24. DDR2 Memory Clock Topology Table Traces TL1 Description Breakout Layer Min Length Maximum Length Trace Width Spacing Micro strip 0.05" 0.5" 4 Mils >=3.5 Mils Spacing to nearest signals TL2 Lead-in Micro strip 0.5" 1.8" 4 Mils >=7 Mils >= 20 mils TL3 Between Devices Micro strip 0.1" 0.8" 4 Mils >=7 Mils >= 20 mils TL4 Device Breakout Micro strip 0.05" 0.2" 4 Mils >=3.
5.6.2.2 Address, Command and Control Table 5-25.
Table 5-26. DDR2 Address, Command, and Control Topology Table Traces Description TL1 Breakout Layer Min Length Maximum Length Trace Width Spacing Micro strip 0.05" 0.5" 4 Mils >=4 Mils TL2 Lead-in Micro strip 0.5" 1.3" 4 Mils >=10 Mils TL3 Breakout Micro strip 0.05" 0.5" 4 Mils >=4 Mils TL4 Between Devices Micro strip 0.1" 0.8" 4 Mils >=10 Mils TL5 Device Breakout Micro strip 0.05" 0.
5.6.2.3 Data and Data Strobe Signals – DQ/DM/DQS Table 5-27. Data and Strobe Signals – DQ/DM/DQS Parameter Routing Guidelines Signal Group DQ/DM/ DQS Reference Plane Recommended layer Route over unbroken ground plane. Micro-strip routing. Breakout width and spacing 4 mils width on 4mils spacing Trace Impedance 55 Ω +/- 10% Trace Spacing (Edge to edge) Within group (byte lane) >=10 mils. >20 mils from any other clock/CMD/Control/DQ/DQS groups Termination No External Termination required.
5.7 VREF Circuit Figure 5-13 shows the DDR2/3 VREF circuit. A simple resistor divider with one percent or better accuracy is used to generate DDR2/3 VREF power. The DDR2/3 VREF is a low-current source (supplying input leakage and small transients). It must track 50 percent of DDR power well over voltage, temperature, and noise. A single source will be used for VREF to eliminate any variation and tracking of multiple generators. Figure 5-13.
5.8 Miscellaneous Signals Design Guidelines The DDR2/3 interface has two calibration balls: RCOMPPU, RCOMPPD. RCOMPPD should be connected through external 80.6 Ω ± 1% calibration resistors to GND. RCOMPPU must be connected through external 80.6 Ω ± 1% calibration resistors to DDR power well. Please match RCOMPPU and RCOMPPD traces inter and intra channel to 3mm. Please keep the trace length under 30mm to minimize the added resistance.
6 Video Output Interfaces This chapter provides major video interfaces design guidelines on Intel® Atom™ processor CE4100-based board. • • • VDAC analog Interfaces One HDMI/DDC transmitter Interfaces Multiple Transport Stream Interfaces 6.1 Video DAC Interface The Video encoder unit supports the traditional analog interfaces (Composite Video, Component Video and S-Video). The component video can support up to 1080P resolution with YPrPb format.
General layout design guide • • • • • • • • • Dedicatedly isolated analog Ground reference plane is required for the whole VDAC interface. Achievable shortest on-board VDAC trace length is preferred. All trace impedance is 55 Ω +/- 10% after the buffer/amplifier. Keep transmission lines as short as possible. Connect all the DAC grounds (analog) together by wide traces close to Video Buffer / Connector. Do not place any extra stubs or probe points on the Video DAC section.
Figure 6-1. VDAC application Model 1: VDAC with Integrated Filter/Amplifier * Split 75OHM video termination to match the board transmission line at the filter side and the rest at the connector side. A single 75OHM can be used if the board trace is less than 1”. VDACDOUT_P/M 1.1k 6.1.1.2 Passive Filter Configuration In this configuration, an analog reconstruction filter is used instead of a buffer (see Figure 6-2). This configuration requires the following changes: • • • • • • VBG_EXTR_VDAC @ 1.
Figure 6-2. VDAC application Model 2: VDAC with Discrete Filter VDACDOUT_P/M 1.
The passive configuration has not been validated, but is documented here as a possible cost-saving solution with the following caveats: • • • • This configuration also requires a 75 Ω termination in the TVs that require a standard 75 Ω video cable for connecting to the TV. There is a possibility of damage to the chip when the power supply’s connection to ground is removed, because of transients on the connecter/cable (due to the removal of the isolation buffer/amplifier).
Figure 6-4. VBG_EXTR_VDAC Connection Figure 6-4 provides an illustration of the recommended shielding trace connection. 75 Ω is achievable by routing microstrip on layer 1 while referring to layer 3. 6.1.1.4 Video DAC Trace Separation Use the following separation guidelines for the Video DAC interface. Figure 6-5 provides an illustration of the recommended trace spacing. • • • • • Maintain parallelism between VDAC_P and VDAC_N signals with the trace spacing needed to achieve 37.
6.1.2 Video Calibration Circuit The Intel® Atom™ processor CE4100 includes an integrated Video Calibration function. Calibration is done to counteract the process related mismatches in the VDAC circuits so that the full scale voltage can meet the +/- 5% tolerance. The video calibration function asks for different termination on the platform. When the calibration function is enabled, the termination is 1.
6.2 HDMI Transmitter Interface The Intel® Atom™ processor CE4100 has an HDMI/DVI version 1.3 compliant transmitter interface, with HDCP. An HDMI cable has four differential pairs that carry AV data and clock over a Transition Minimized Differential Signaling (TMDS) protocol. In addition, HDMI carries a VESA DDC (Enhanced Display Data Channel) channel. DDC uses I2C protocol and is used for configuration and status exchange between the HDMI driver and HDMI receiver.
6.2.1 Detailed HDMI Routing Example Figure 6-9.
Table 6-2. HDMI Transmitter Routing Guidelines for the 1080 Stack-up Parameter Routing Guidelines Signal Group HDMI_TDMS_DP[0:2], HDMI_TDMS_DN[0:2] HDMI_TDMS_CLKP, HDMI_TDMS_CLKN Reference Plane Solid Gnd Referenced, Accompanying GND via is required for each signal net at layer transition, though signal layer transition should be avoided. Layer Assignment MicroStrip (top or bottom layer) (top layer routing is preferred) Trace Impedance (Z0) 100 Ω +/-10% (differential) nominal Trace width 4.
6.2.2 HDMI ESD Protector Routing Suggestions Due to the extra load of parasitic capacitance Cload (typically around 0.1pF from each Io pin to ground), a large impedance discontinuity might occur that significantly degrades the signal integrity of the high–speed differential channels, such as HDMI video quality. This section introduces layout suggestions for HDMI ESD protection and connector area routing to improve HDMI ESD issues.
Figure 6-10. Using an IP4777CZ38 ESD Device Example – 6+ Layer Stack-up. HDMI Connector S0 S1 Ha ~= 250mil, or about 1/10 wavelength @ 2.5GHz IP4777CZ38 S0 S1 S1 S1 S1=S0 S0~= 25.5mil S0 S1 Hb ~= 250mil, or about 1/10 wavelength @ 2.
Figure 6-11. Using an IP4777CZ38 ESD Device Example – 4 Layer Stack-up. HDMI Connector S0 S1 Ha ~= 250mil, or about 1/10 wavelength @ 2.5GHz IP4777CZ38 S0 S1 S1 S1 S1=S0 S0~= 25.5mil S0 S1 Hb ~= 250mil, or about 1/10 wavelength @ 2.
Notes: • • • There is a GND trench on layer 2 as indicated in the purple dot rectangle. Layer 3 is also GND. All Blue dots are GND through vias connecting the GND locally among all layers. The length of two segments (Ha and Hb) is around 1/10 wavelength @ 2.5GHz, which is about 150 Ω differential HDMI TMDS signal traces above and below the ESD protection pins. The purpose for these two segments is to compensate the parasitic capacitance introduced by each ESD protection device pins.
Figure 6-12. Using a CM2030 or TPD12S521 ESD Device Example – 6+ Layer Stackup.
Figure 6-13. Using a CM2030 or TPD12S521 ESD Device Example – 4 Layer Stackup.
Notes: • • • There is a GND trench on layer 2 as indicated in the purple dot rectangle. Layer 3 is also GND. All Blue dots are GND through vias connecting the GND locally among all layers The length of two segments (Ha and Hb) is around 1/10 wavelength @ 2.5GHz, which is about 150 Ω differential HDMI TMDS signal traces above and below the ESD protection pins. The purpose for these two segments is to compensate the parasitic capacitance introduced by each ESD protection device pins.
6.3.1 TS Interface Routing Topology Example The topology shown in Figure 6-15 is the same for the input transport stream clock, transport stream data [D0:D1], and the associated control signals. The trace widths provided here assume all the trace impedances are 55 Ω +/- 10% (4 mile trace). Figure 6-15. TS Interface Routing Topologies Traces TL1 Description Layer Min Length Max Length Trace Width Spacing 3384 breakout Micro strip 0.1” 0.5” 4 Mils >=10Mils TL2 Lead in Micro strip 1.0” 8.
7 Audio Interfaces 7.1 Overview The Intel® Atom™ processor CE4100 supports one 7.1 I2S output, one stereo I2S output, and one S/PDIF output. All of these outputs can be functioning simultaneously. On the input side, it will support one stereo I2S input. 7.2 I2S Audio Input Interface The I2S audio capture port provides the bit clock and the WS sample rate clock derived from the Fs*768=36.864 MHz I2S system clock (AUDIO_CLOCK). This interface includes I2S_BCK_IN, I2S_LRW_IN and I2S_SDATA_IN.
7.3 I2S Audio Output Interface This interface includes I2S0 interface (I2S0_BCK_OUT, I2S0_LRWS_OUT and I2S0_SDATA_OUT) and I2S1 interface (I2S1_BCK_OUT, I2S1_LRWS_OUT and I2S1_SDATA_OUT0~3). Figure 7-2. I2S Audio Output Interconnects Topology The Audio Output channels are designed to transfer the decoded audio samples between the unified memory buffers and audio digital-to-analog converters with I2S interfaces.
7.4 S/PDIF Audio Interface This S/PDIF interface supports the IEC60958 standard. This is a serial unidirectional selfclocking interface. The interface supports linear PCM sampling rates of 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, and 192 kHz with 24-bit stereo data samples. Figure 7-3. S/PDIF Audio Output Interconnects Topology Table 7-3. S/PDIF Output Interconnects Traces Layer Min Length Max Length Trace: Width/Spacing Spacing from other signals w_TL1 Break out 0.1” 0.
8 Other Interfaces 8.1 Serial ATA (SATA) Interface The Intel® Atom™ processor CE4100 contains two SATA ports capable of independent DMA operation. The SATA controllers are completely software transparent with the IDE interface, while providing a lower pin count and higher performance. The SATA interface supports data transfer rates up to 3.0 Gb/s. Note Please also refer to www.serialata.org for detail SATA design guides.
8.1.1 SATA Routing Guidelines The SATA interface has a point-to-point topology as shown in Figure 8-1. Only one SATA port is shown in the figure. Figure 8-1. Serial ATA Topology Sodaville Tx Package TL=TL1+TL2+TL3 Via Break out (MS) Board (MS Board Via (MS AC Cap Tx Package Via Break out (MS TL1 Board (MS TX Board Via (MS TL2 TL3 SATA CONN.
8.1.1.1 Serial ATA Trace Separation Use the following separation guidelines for the SATA interface. Figure 8-2 provides an illustration of the recommended trace spacing. • • • Maintain parallelism between SATA differential signals with the trace spacing needed to achieve 100-Ω ± 10% differential impedance. Deviations will normally occur due to package breakout and routing to connector pins. Ensure that the amount and length of the deviations are kept to the minimum possible.
8.1.1.2 Serial ATA Trace Length Guidelines Table 8-1. Serial ATA Differential Pair Routing Guidelines for the 1080 Stack-up Parameter Routing Guidelines Signal Group SATA[0:1]_Txp, SATA[0:1]_Txn SATA[0:1]_Rxp, SATA[0:1]_Rxn Reference Plane Gnd Referenced, Ground vias are required when signal net has layer transition. Layer Assignment Micro Strip (top or bottom layer) Trace Impedance (Z0) 100 Ω +/-10% (differential) (nominal 55 Ω, if it is single-end) nominal Trace width (W)4.
8.1.1.3 Serial ATA AC Coupling Requirements The Intel® Atom™ processor CE4100 requires AC coupling capacitors for both the Tx and Rx SATA differential pairs, see Figure 8-1. The series capacitors may be placed at any point on the traces between the processor and the Serial ATA connector. The general place for these AC capacitors is about 1 inch to the SATA.
8.1.2 Terminating Unused SATA Signals If the SATA port(s) will not be implemented on the platform, SATAx_RX[P/N] and SATAx_TX[P/N] signals may be left unconnected (where ‘x’ is the port number left as no connect).
8.2 USB 2.0 The Universal Serial Bus (USB) is a cable bus that supports data exchange between a host computer and a wide range of simultaneously accessible peripherals. The attached peripherals share USB bandwidth through a host-scheduled, token-based protocol. The bus allows peripherals to be attached, configured, used, and detached while the host and other peripherals are in operation. The Intel® Atom™ processor CE4100 supports dual USB 2.0 host ports to connect variety of devices.
8.2.1.1 USB 2.0 Trace Separation Use the following separation guidelines. • • • • Maintain parallelism between USB differential signals with the trace spacing needed to achieve 90-Ω differential impedance. Deviations will normally occur due to package breakout and routing to connector pins. Just ensure the amount and length of the deviations is kept to the minimum possible. Use an impedance calculator to determine the trace width and spacing required for the specific board stack-up being used.
Table 8-4. USB Channel Routing Guidelines Parameter Routing Guidelines Figure Signal Group USB[1:0]P_P, and USB[1:0]P_N Reference Plane Ground Referenced, Ground vias are required when signal net has layer transition. Layer Assignment Top layer or bottom layer (Micro Strip) Trace Impedance (Z0) 90 Ω +/-10% (differential) nominal Trace width (W) 4 mil –micro strip Nominal Trace Spacing Intra-pair Trace Spacing (fixed):4.
8.2.1.2 USBRBIAS/USBRBIASN Connection Intel recommends that designers short the USBRBIASP and the USBRBIASN pins at the package, and then rout the shorted pins to one end of a 22.6 Ω ±1% resistor to ground. Place the resistor within 500 mils of the processor. Avoid routing next to clock pins. Figure 8-7. USBRBIAS/USBRBIASN Connection Table 8-5.
8.2.1.3 USB Power Sequence With more and more USB devices used for different purposes, there is a potential issue that a USB device might not be detected during power cycles. Intel recommends adding a delay circuit or designing the power sequence circuit in the USB power interface to prevent this issue. On the development platform, the PIC (external microcontroller) is used to control the PIC_USB_EN# signals, which are used to enable 5V VBUS_USB power rails on USB connectors.
8.3 Gigabit Ethernet The Gigabit Ethernet Media Access Controller (GbE MAC) is based on Intel’s fourth generation gigabit MAC. The GbE MAC provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications. The controller is capable of transmitting and receiving data rates of 10/100/1000 Mbps. Through the GbE MAC interface, the Intel® Atom™ processor CE4100 can be connected to an external PHY, which can support Reduced Ethernet (RMII) and Reduced GMII (RGMII).
Figure 8-9. GBE Interface Clock Signal Design Example RMII RGMII 25MHz 25MHz RMII PHY RGMII PHY (RTL8201n) (RTL8211b) 125MHz GBE_REFCLK Not Used 1000/100/10 125/25/2.5MHz GBE_REFCLK GBE_TXCLK GBE_TXCLK Intel® Atom™ processor CE4100 Intel® Atom™ processor CE4100 RGMII: Strapping must be set to use external clock mode 50MHz RMII: Strapping is set as internal clock mode Note: The Intel® Atom™ processor CE4100 can provide a 50-MHz clock source to RMII PHY by GBE_TXCLK signal.
Figure 8-12. GBE_TXCTL Figure 8-13. GBE_REFCLK Table 8-6. GBE Transmitter Routing Guidelines Traces Description Layer Min Length Max Length Trace Width Spacing SDV Breakout Micro strip 0.1” 0.5” 4 Mils >=4 Mils TL2 Lead-in Micro strip 0.5” 6.5” 4 Mils >=10 Mils TL3 breakin Micro strip 0.5” 1” 4 Mils >=4 Mils TL1 Length match ±0.25” Notes TL1+TL2+TL3 Notes: • GBE TX signal group: GBE_TXCLK, and GBE_TXDATA<0-3>. Match all signals with in +/- 0.25” respect to its clock.
Figure 8-14. GBE_RXDATA<0~3> and GBE_RXCLK Table 8-7. GBE RX Routing Guidelines Traces TL1 TL2 TL3 Length match Description Layer Min Length Max Length Trace Width Spacing SDV Breakout Micro strip 0.1” 0.5” 4 Mils >=4 Mils Lead-in 1 Micro strip 0.5” 6.5” 4 Mils >=10 Mils GBE Breakout Micro strip 0.1” 0.5” 4 Mils >=4 Mils ±0.25” Notes TL1+TL2+TL3 Notes: • GBE RX signal group: GBE_RXCLK, GBE_RXCTL, and GBE_RXDATA<0-3>. Match all signals with in +/0.25”respect to its clock.
8.4 Expansion Bus Interface Guidelines The expansion bus is a general-purpose synchronous bus that can host 16-bit and 8-bit memory devices or peripherals such as NOR flash and other peripherals such as Cable Cards and front panel controllers. The expansion bus includes a 26-bit address bus and two 8-bit wide data paths. It maps transfers between the internal backbone bus and the external devices. The bus controller has an address decoder, which generates up to four device select strobes.
8.4.1 Expansion Bus Chip Select The Expansion Bus includes a 26-bit address bus and two 8-bit wide data paths. It maps transfers between the internal Backbone bus and the external devices. The bus controller has an address decoder that generates up to four device select strobes. The four devices together take 256 MB of contiguous IA-32 address space.
8.4.2 Expansion Bus Address, EXP_ALE and EXP_IO_WRB The address bus is multiplexed. Address bus bits [15:0] are dedicated; address bits [23:15] are multiplexed onto EXP_DATA_A[7:0] and must be captured using an external address latch controlled by EXP_ALE; address bits [25] and [24] are multiplexed onto EXP_IO_WRB and EXP_IO_RDB, respectively, and must also be latched externally. Figure 8-17 shows the topology for the Address bus. Figure 8-17.
8.4.3 Data Bus A EXP_DATA_A and EXP_DATA_B, EXP_DATA_A is intended for access to “insecure” devices, and no special measures are taken to prevent the access to its lines on the PCB. For instance, this bus may be used to communicate with the boot PROM or any other external flash devices, LEDs, front panel controls. Figure 8-18. Data Bus DA<0-7> Topology Table 8-10. Data Bus_A Topology list Traces Max Length Trace: Width/Spacing Spacing from other signals Layer Min Length w_TL0 Breakout 0.1” 0.
8.4.4 Data Bus B and Control Signals Data bus B has a different topology than data bus A. The second bus (EXP_DATA_B) section may be used, if desired, to access “secure” devices, like an external ROM which contains sensitive code. This data bus is isolated from the EXP_DATA_A bus. The ROM should be packaged in BGA, and the data lines may be buried in internal layers of the PCB to deter access and data logging.
8.5 NAND Flash The NAND Flash Controller used in the Intel® Atom™ processor CE4100 is licensed from Denali Corporation. 8.5.1 NAND Flash Interface Diagram Figure 8-20. NAND Flash Controller NAND_CE_N[3:0] NAND_ALE NAND_CLE NAND Controller Core NAND PADS NAND_WE_N NAND_RE_N NAND_IO[7:0] NAND_RY_BY_N NAND_CLK_X_OUT NAND_CLK_X_IN 8.5.
8.5.3 Traces NAND_IO Topology Max Length Trace: Width/Spacing Spacing from other signals Layer Min Length w_TL0 Breakout 0.1” 0.5” 4 mils >=4 mils w_TL1+w_TL2 Micro strip 0.5” 6.5” 4 mils >=8 mils Notes: • Match all signals within 0.25”, including NAND_WE_N, NAND_RE_N, NAND_CLE and NAND_ALE signals. • All traces impedance required to be 55 Ω+/- 10%. • All signals should be referenced to ground. Reference to unbroken power plane is also accepted. • Rtt_rcv: 1.8 KΩ +/-5%.
8.5.4 Traces NAND_WE_N, NAND_RE_N, NAND_CLE and NAND_ALE Topology Max Length Trace: Width/Spacing Spacing from other signals Layer Min Length w_TL0 Breakout 0.1” 0.5” 4 mils >=4 mils w_TL1+w_TL2 Micro strip 0.5” 6.5” 4 mils >=8 mils Notes: • Match all signals within 0.25”, including all NAND_IO signals. • Keep NAND_WE_N and NAND_RE_N signal min 2X spacing (> 16 mils) from the other nets. • All traces impedance required to be 55 Ω+/- 10%. • All signals should be referenced to ground.
8.5.5 Traces NAND_CE_N Topology Max Length Trace: Width/Spacing Spacing from other signals Layer Min Length w_TL0 Breakout 0.1” 0.5” 4 mils >=4 mils w_TL1+w_TL2 Micro strip 0.5” 10” 4 mils >=8 mils Notes: • All trace impedance required to be 55 Ω+/- 10%. • All signals should be referenced to ground. Reference to unbroken power plane is also accepted.
8.5.6 NAND_RY_BY_N Signal Recommendation NAND1 Sodaville Traces Layer Min Length Max Length Trace: Width/Spacing Spacing from other signals w_TL0 Breakout 0.1” 0.5” 4 mils >=4 mils w_TL1 Micro strip 0.5” 5.0” 4 mils >=8 mils w_TL2 Micro strip 0.1” 1.0” 4 mils >=8 mils w_TL3 Micro strip 0.1” 0.5” 4 mils >=8 mils Notes: • Topology shown is for NAND_RY_BY_N between SDV and the first NAND (in socket) only. • All trace impedance required to be 55 Ω +/- 10%.
8.5.7 NAND_CLK_X_OUT/IN Topology Traces Layer Param Min Length Max Length Trace: Width/Spacing Spacing from other signals w_TL0 Breakout Len0 0.1” 0.5” 4 mils >=4 mils w_TL1 Micro strip Len1 0.5” 4.5” 4 mils >=10 mils w_TL2 Micro strip Len2 0.5” 5” 4 mils >=10mils Notes 1, 2, 3 1, 2, 3 1, 2, 3 Notes: • All trace impedance required to be 55Ω +/- 10%. • All signals should be referenced to ground. Reference to unbroken power plane is also accepted.
8.6 I2C* Interface The I2C Bus Interface Unit allows the Intel® Atom™ processor CE4100 to serve as a master device residing on the I2C bus. The I2C bus is a serial bus developed by Philips Corporation consisting of a two-pin interface. Note Please also refer to www.semiconductors.philips.com for detail I2C electrical design guide. The I2C bus allows the Intel® Atom™ processor CE4100 to interface to other I2C peripherals and microcontrollers for system management functions.
8.7 UART Interface There are two high-speed UART interfaces in the Intel® Atom™ processor CE4100. One is used for debug purposes, and another may be used to drive the external low-speed modem chip, which will transmit the billing information in STB applications. UART0 is full function UART port, and may be connected to an external modem chip. UART1 is not full function; only the RXD and TXD pins are bonded out. The maximum baud rate supported in the UART is 921.6 Kbps.
8.7.1 UART0_RXD Signal Recommendation Figure 8-22. UART0_RXD signal Topology Table 8-13. UART0_RXD signal Topology Traces Max Length Trace: Width/Spacing Spacing from other signals Layer Min Length w_TL0 Breakout 0.1” 0.5” 4 mils >=4 mils w_TL1+w_TL2 Micro strip 1” 15” 4 mils >=8 mils Notes: • All traces impedance required to be 55 Ω +/- 10%. • Simulation data based on the Intel® Atom™ processor CE4100 IBIS model. • All signals should be referenced to ground.
8.7.2 UART0_DSRB Signal Recommendation Figure 8-23. UART0_DSRB signal Topology Table 8-14. UART0_DSRB signal Topology Traces Max Length Trace: Width/Spacing Spacing from other signals Layer Min Length w_TL0 Breakout 0.1” 0.5” 4 mils >=4 mils w_TL1+w_TL2 Micro strip 0.5” 20” 4 mils >=8 mils Notes: • All traces impedance required to be 55 Ω +/- 10%. • Simulation data based on Cin=10pF (no IBIS models). • All signals should be referenced to ground.
8.8 GPIO Interface The General Purpose I/O interface provides additional flexibility to system designers. GPIO[4:0] and GP_9 are dedicated GPIO pins and are not multiplexed with any other function. The remaining GPIO pins are multiplexed with various functions. The MUX function is controlled by the GPIO_MUXCNTL register in this unit.
Figure 8-24. GPIO Interface Topology Table 8-15. GPIO Interface list Traces Max Length Trace: Width/Spacing Spacing from other signals Layer Min Length w_TL0 Breakout 0.1” 0.5” 4 mils >=4 mils w_TL1+w_TL2 Micro strip 1” 15” 4 mils >=8 mils Notes: • Match W_TL1 within 0.25 inch. • All traces impedance required to be 55 Ω+/- 10%. • Simulation data based on IBIS model. • All signals should be referenced to ground. Reference to unbroken power plane is also accepted.
8.9 SPI Serial Interface The SPI serial interface on the Intel® Atom™ processor CE4100V provides two-channel (two chip selects), 3wire serial input/output interface to connect to SPI-compatible devices directly, such as audio DACs and frequency synthesizers in television tuners. The SPI interface can support up to 16 bits. The 4-bit data size register (DSS) is used to select the size of the data transmitted and received by the Synchronous Serial Port (SSP). The data can be set from 4 bits to 16 bits.
8.9.2 SPI_MISO Routing Recommendation Figure 8-25. SPI SPI_MISO signal Topology Sodaville Table 8-17. SPI SPI_MISO signal Topology list Traces Layer Min Length Max Length Trace: Width/Spacing Spacing from other signals w_TL0 Breakout 0.1” w_TL1 Micro strip 0.5” 10.0” 4 mils >=8 mils w_TL2 Micro strip 0.5” 5.0” 4 mils >=8 mils w_TL3/4 Micro strip 0.5” 5.0” 4 mils >=8 mils 0.5” 4 mils >=4 mils Notes: • All traces impedance required to be 55 Ω+/- 10%.
8.9.3 SPI_MOSI and SPI_SCK Routing Recommendation Figure 8-26. SPI_MOSI and SPI_SCK signal Topology Load 1 Load 2 Load 3 1K Table 8-18. SPI_MOSI and SPI_SCK signal Topology list Traces Max Length Trace: Width/Spacing Spacing from other signals Layer Min Length w_TL0 Breakout 0.1” 0.5” 4 mils >=4 mils w_TL1+w_TL2 Micro strip 0.1” 9” 4 mils >=8 mils w_TL3/4/5 Micro strip 0.1” 6.0” 4 mils >=8 mils Notes: • All traces impedance required to be 55 Ω+/- 10%.
8.9.4 SPI_SS Signal Routing Recommendation Figure 8-27. SPI_SS signal Topology Table 8-19. SPI_SS signal Topology list Traces Max Length Trace: Width/Spacing Spacing from other signals Layer Min Length w_TL0 Breakout 0.1” 0.5” 4 mils >=4 mils w_TL1+w_TL2 Micro strip 0.5” 20” 4 mils >=8 mils Notes: • All traces impedance required to be 55 Ω+/- 10%. • Simulation data based on Cin=5pF (no IBIS models). • All signals should be referenced to ground.
8.10 Smart Card Interface The Intel® Atom™ processor CE4100 has two identical and independent smart card interfaces. The smart card connector can be directly connected to the Intel® Atom™ processor CE4100. When the card is inserted, it activates the card presence switch in the card socket, which is periodically polled by the software via the SC_INSERT pin.
8.10.1 Smart Card Signal Routing Recommendation Figure 8-28. SC Signal Topology Table 8-21. SC0_INS_GP[7] and SC1_INS_GAP[11] Signal Topology List Traces Max Length Trace: Width/Spacing Spacing from other signals Layer Min Length w_TL0 Breakout 0.1” 0.5” 4 mils >=4 mils w_TL1+w_TL2 Micro strip 1” 20” 4 mils >=8 mils Notes: • Simulation data based on Cin=10pF (no IBIS models) • All traces impedance required to be 55 Ω+/- 10%. • All signals should be referenced to ground.
9 High Definition Video Capture (HDVCAP) The High Definition Video Capture (HDVCAP) unit is capable of real-time capturing of digital component video that complies with three industry-accepted standards for digital video interfaces. These include EIA/CEA-861-D, ITU-R BT.656-4 and ITU-R BT.1120-5. In addition, 8-bit, 10-bit and 12-bit YCbCr and RGB are supported. Please refer to the EIA/CEA-861-D standard for a complete description of the resolutions and timing.
Table 9-1.
9.2 HDVCAP Routing Topology 9.2.1 HDVCAP Design Topology 1 Figure 9-2. HDVCAP Signal Topology With NOR Boot NOR FLASH TL4 Strap SW Sodaville Break Out TL1 TL5 TL3 MUX HDMI RX TL2 33 TL6 TL7 Table 9-2. HDVCAP Signal Length Table Traces Min Length Max Length Description Layer TL1 SDV Breakout Micro strip 0.3” 0.7” TL2 Lead-in Micro strip 2.5” TL3 Lead-in Micro strip 0.
9.2.2 HDVCAP Design Topology 2 Figure 9-3. HDVCAP Signal Topology With NAND Boot Table 9-3. HDVCAP Signal Length Table Traces Min Length Max Length Trace Width Description Layer Spacing TL1 SDV Breakout Micro strip 0.3” 0.7” 4 Mils >=4 Mils TL2 +TL1 Lead-in Micro strip 1” 2.5” 4 Mils >=8Mils Notes: • • • • 33 Ω resistor should be close to HDMI Rx Chip ( TL2 << TL1) . Please double check the HDMI Rx chip datasheet for this design requirement.
10 Platform Clock Design Guidelines The Intel® Atom™ processor CE4100 needs an external (on-board) clock resource to provide clocks for AV, SATA, HPLL, RGMII Ethernet and USB. Figure 10-1. Clock Diagram Example.
The diagram below shows the clocking scheme example on the development platform. Figure 10-2.
10.1 Reference Clock Routing Guidelines 10.1.1 CK505 Clock Topology The HPLL, SATA, and USB reference clocks generate from CK505. The diagram below shows the CK505 to the Intel® Atom™ processor CE4100 clock channel Topology. CK505 Clock Routing Guideline The HDMI, VDC_CLK2, CLK27M and Audio reference clocks generate from IDT6V49061. Only the HDMI Clock is differential signal. Others are single-ended signals .
Table 10-1. CK505 Clock Routing Guidelines Parameters Routing Guidelines Signal Group HPLL_REF_CLKP/N, SATA_CLKP/N, USB_CLKP/N Reference Plane Solid Ground Referenced. Accompanying GND via is required for each signal net, if signal net layer transition is not avoidable. Layer Assignment MicroStrip (Top or Bottom layer) Trace Impedance (Z0) 100 Ω +/-10% (Differential) Serial Terminal Rs 33 Ω +/-5% Nominal Trace width 4.0 mils (single) & 4.0x7.0 (Diff.
Figure 10-4. IDT6V49061 HDMI Reference Clock Topology IDT6V49601 TL1 TL2 RS=33+/-5% RT=55+/-5% via TL3 Sodaville TL0 Notes: • • At least 3 times of inter-pair space to the other signals to mitigate Xtalk. Trace length skew in the differential pair is within 50mils. Table 10-2. IDT6V49061 Clock Routing Guidelines Parameters Routing Guidelines Signal Group HDMI_REF_CLKP/N Reference Plane Solid Ground Referenced.
10.1.2.2 Audio and VDC Clock Input Design Example The HDMI, VDC_CLK2, CLK27M and Audio reference clocks generate from IDT6V49061. Only the HDMI Clock is differential signal. Others are single-ended signals .The diagram below shows the IDT6V49061 HDMI Clock to the Intel® Atom™ processor CE4100 clock channel Topology. Figure 10-5. IDT6V49061 Audio and VDC CLK Topology IDT6V49601 TL1 TL2 via TL3 Sodaville Table 10-3.
10.2 Audio Reference Clock Output Routing Recommendation Clock Name au_ref_clk Unit Frequency Audio reference clock for internal clock generation in AU Notes 36.8640, 33.8688, 24.576, 22.5792 MHz Figure 10-6. Audio_clk Signal Topology Table 10-4. Audio_clk Signal Topology List Traces Max Length Trace: Width/Spacing Spacing from other signals Layer Min Length w_TL0 Breakout 0.1” 0.5” 4 mils >=4 mils w_TL1+w_TL2 Micro strip 0.
10.3 VCXO Mode Design Guidelines The Voltage-controlled Crystal Oscillator’s (VCXO) output frequency changes in proportion to the application of any input control voltage. The VCXO is used to provide synchronization of the input Transport Stream (TS) to the AV output. The rendered frame rate of the AV must match the frame rate of the input TS to prevent frame drops or duplications and the audio and video defects associated with them.
How to test this VCXO tuning on board: 1. The VCXO should generate 27MHz with the control voltage in the midpoint of control range. 2. While Sigma-delta register with half of the maximum range is programmed, the voltage on the VCXO control pin should be +1.6V. 3. Check the waveform on the modulator’s output. Clock divider register might be needed to appropriately program VCXO to meet correct frequency. 4. Check the control voltage at 90% and 10% of full scale, which should be around +2.8V and +0.
