Flat Panel Television User Manual
Table Of Contents
- TOC
- 01-Overview
- 02-Address Space
- 03-Addressing Modes
- 04-Control Registers
- 05-Interrupt Structure
- 06-Instruction Set
- 07-Clock and Power Circuits
- 08-RESET
- 09-IO PORTS
- 10-BASIC TIMER and TIMER 0
- 11-Timer1
- 12-CounterA
- 13-Timer2
- 14-EMBEDDED Flash Memory Interface
- 15-Low Voltagge Detector
- 16-Electrical Data
- 17-Mechanical Data
- 18-Flash MCU
- 19-Development Tool
- TOC.pdf
S3F80P5_UM_ REV1.00 CONTROL REGISTERS
IMR — Interrupt Mask Register DDH Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
x x x x x x x x
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode
Register addressing mode only
.7 Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.7–P0.4
0 Disable (mask)
1 Enable (un-mask)
.6 Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.3–P0.0
0 Disable (mask)
1 Enable (un-mask)
.5
Not used for S3F80P5
.4 Interrupt Level 4 (IRQ4) Enable Bit; External Interrupts P2.0
0 Disable (mask)
1 Enable (un-mask)
.3 Interrupt Level 3 (IRQ3) Enable Bit; Timer 2 Match or Overflow
0 Disable (mask)
1 Enable (un-mask)
.2 Interrupt Level 2 (IRQ2) Enable Bit; Counter A Interrupt
0 Disable (mask)
1 Enable (un-mask)
.1 Interrupt Level 1 (IRQ1) Enable Bit; Timer 1 Match or Overflow
0 Disable (mask)
1 Enable (un-mask)
.0 Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match or Overflow
0 Disable (mask)
1 Enable (un-mask)
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