Flat Panel Television User Manual
Table Of Contents
- TOC
- 01-Overview
- 02-Address Space
- 03-Addressing Modes
- 04-Control Registers
- 05-Interrupt Structure
- 06-Instruction Set
- 07-Clock and Power Circuits
- 08-RESET
- 09-IO PORTS
- 10-BASIC TIMER and TIMER 0
- 11-Timer1
- 12-CounterA
- 13-Timer2
- 14-EMBEDDED Flash Memory Interface
- 15-Low Voltagge Detector
- 16-Electrical Data
- 17-Mechanical Data
- 18-Flash MCU
- 19-Development Tool
- TOC.pdf
ADDRESS SPACE S3F80P5_UM_ REV1.00
Bank1
D0H
CFH
E0H
DFH
C0H
Bank 0
System and
Peripheral
Control Register
(Register Addressing
Mode)
System Register
(Register Addressing
Mode)
Working Register
(Working Register
Addressing only)
FFH
Set 1
FFH
Set 2
C0H
Page 0
General Purpose
Data Register
(Indirect Register or
Indexed Addressing
Modes or
Stack Operations)
256
Bytes
E0H
Page 0
Prime
Data Register
(All Addressing
Mode)
BFH
192
Bytes
00H
64
Bytes
32
Bytes
32
Bytes
Figure 2-3. Internal Register File Organization
2-6