Flat Panel Television User Manual
Table Of Contents
- TOC
- 01-Overview
- 02-Address Space
- 03-Addressing Modes
- 04-Control Registers
- 05-Interrupt Structure
- 06-Instruction Set
- 07-Clock and Power Circuits
- 08-RESET
- 09-IO PORTS
- 10-BASIC TIMER and TIMER 0
- 11-Timer1
- 12-CounterA
- 13-Timer2
- 14-EMBEDDED Flash Memory Interface
- 15-Low Voltagge Detector
- 16-Electrical Data
- 17-Mechanical Data
- 18-Flash MCU
- 19-Development Tool
- TOC.pdf
TIMER 2 S3F80P5_UM_ REV1.00
Timer2 Counter High-Byte Register (T2CNTH)
E4H , Set 1, Bank 1, Read-only
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Reset Value: 00H
Timer 2 Counter Low-Byte Register (T2CNTL)
E5H , Set 1, Bank 1, Read-only
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Reset Value: 00H
Timer 2 Data High-Byte Register (T2DATAH)
E6H , Set 1, Bank 1, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Reset Value: FFH
Timer 2 Data Low-Byte Register (T2DATAL)
E7H , Set 1, Bank 1, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Reset Value: FFH
Figure 13-5. Timer 2 Registers (T2CNTH, T2CNTL, T2DATAH, T2DATAL)
13-6