Flat Panel Television User Manual
Table Of Contents
- TOC
- 01-Overview
- 02-Address Space
- 03-Addressing Modes
- 04-Control Registers
- 05-Interrupt Structure
- 06-Instruction Set
- 07-Clock and Power Circuits
- 08-RESET
- 09-IO PORTS
- 10-BASIC TIMER and TIMER 0
- 11-Timer1
- 12-CounterA
- 13-Timer2
- 14-EMBEDDED Flash Memory Interface
- 15-Low Voltagge Detector
- 16-Electrical Data
- 17-Mechanical Data
- 18-Flash MCU
- 19-Development Tool
- TOC.pdf
COUNTER A S3F80P5_UM_ REV1.00
MUX 8-Bit Down Counter
MUX
Counter A Data
Low Byte Register
IRQ2
(CAINT)
NOTE:
The value of the CADATAL register is loaded into the 8-bit counter when the
operation of the counter A stars. If a borrow occurs, the value of the
CADATAH register is loaded into the 8-bit counter. However, if the next borrow
occurs, the value of the CADATAL register is loaded into the 8-bit counter.
Data Bus
Counter A Data
High Byte Register
CACON.0
(CAOF)
Repeat
Control
CLK
DIV 1
DIV 2
DIV 4
DIV 8
CACON.2
f
OSC
Interrupt
Control
CACON.4-.5
INT. GEN.
To Other Bloc
k
(P3.1/REM)
CACON.3
CACON.6-.7
Figure 12-1. Counter A Block Diagram
12-2