Flat Panel Television User Manual
Table Of Contents
- TOC
- 01-Overview
- 02-Address Space
- 03-Addressing Modes
- 04-Control Registers
- 05-Interrupt Structure
- 06-Instruction Set
- 07-Clock and Power Circuits
- 08-RESET
- 09-IO PORTS
- 10-BASIC TIMER and TIMER 0
- 11-Timer1
- 12-CounterA
- 13-Timer2
- 14-EMBEDDED Flash Memory Interface
- 15-Low Voltagge Detector
- 16-Electrical Data
- 17-Mechanical Data
- 18-Flash MCU
- 19-Development Tool
- TOC.pdf
TIMER 1 S3F80P5_UM_ REV1.00
MUX
16-Bit Up-Counter
(Read-Only)
16-Bit Compatator
Timer 1 High/Low
Buffer Register
MUX
IRQ1
Clear
IRQ1
Match
(note)
NOTE:
Match signal is occurrd only in interval mode.
T1CON. 7-.6
T1CON.2
T1CON.3
Match Signal
T1OVF
Data Bus
Timer 1 Data
High/Low Register
CAOF (T-F/F)
f
OSC
/16
f
OSC
/8
f
OSC
/4
R
OVF
T1CON.3
T1CON.5-.4
T1CON.1
T1CON.0
Figure 11-3. Timer 1 Block Diagram
11-4