Flat Panel Television User Manual
Table Of Contents
- TOC
- 01-Overview
- 02-Address Space
- 03-Addressing Modes
- 04-Control Registers
- 05-Interrupt Structure
- 06-Instruction Set
- 07-Clock and Power Circuits
- 08-RESET
- 09-IO PORTS
- 10-BASIC TIMER and TIMER 0
- 11-Timer1
- 12-CounterA
- 13-Timer2
- 14-EMBEDDED Flash Memory Interface
- 15-Low Voltagge Detector
- 16-Electrical Data
- 17-Mechanical Data
- 18-Flash MCU
- 19-Development Tool
- TOC.pdf
S3F80P5_UM_ REV1.00 TIMER 1
TIMER 1 MATCH INTERRUPT
Timer 1 can also be used to generate a match interrupt (IRQ1, vector F6H) whenever the 16-bit counter value
matches the value that is written to the Timer 1 reference data registers, T1DATAH and T1DATAL. When a match
condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and
up counting resumes from ‘00H’.
In match mode, program software can poll the Timer 1 match/capture interrupt pending bit, T1CON.0, to detect
when a Timer 1 match interrupt pending condition exists (T1CON.0 = “1”). When the interrupt request is
acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F6H must clear
the interrupt pending condition by writing a “0” to T1CON.0.
Match
CTL
T1CON.5
T1CON.4
P3.0
R (Clear)
Pending
(T1CON.0)
Interrupt
Enable/Disable
(T1CON.1)
16-Bit Up Counter
CLK
16-Bit Comparator
Timer 1 High/Low
Buffer Register
Timer 1 Data High/Low
Buffer Register
IRQ1 (T1INT)
Match Signal
T1CON.3
Figure 11-2. Simplified Timer 1 Function Diagram: Interval Timer Mode
11-3