Flat Panel Television User Manual
Table Of Contents
- TOC
- 01-Overview
- 02-Address Space
- 03-Addressing Modes
- 04-Control Registers
- 05-Interrupt Structure
- 06-Instruction Set
- 07-Clock and Power Circuits
- 08-RESET
- 09-IO PORTS
- 10-BASIC TIMER and TIMER 0
- 11-Timer1
- 12-CounterA
- 13-Timer2
- 14-EMBEDDED Flash Memory Interface
- 15-Low Voltagge Detector
- 16-Electrical Data
- 17-Mechanical Data
- 18-Flash MCU
- 19-Development Tool
- TOC.pdf
S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0
MUX
MUXDIV
R
8-Bit Up-Counter
(T0CNT)
8-Bit Compatator
Timer0 Buffer
Register
Bits 5, 4
Bit 0
Bit 1
IRQ0
Clear
Data Bus
Bit 0
IRQ0
OVF
8-Bit Up Counter
(BTCNT, Read-Only)
DIV
R
X
IN
X
IN
OVF
RESE
T
Data Bus
Clear
When BTCNT.4 is set after releasing from
RESET or STOP mode, CPU clock starts.
Match
(2)
Basic Timer Control Register
(Write'1010xxxxB' to disable.)
Bits7, 6
Bits 3, 2
Bit 1
RESET or STOP
(Timer0 Overflow)
Bit 2
(Timer0 Match)
T0PWM
Basic Timer Control Register
Timer0 Control Register
Match Signal
T0CON.3
T0OVF
Data Bus
Timer0 Data Register
(T0DATA)
1/4096
1/8
1/256
1/4096
1/1024
1/128
P3.0/T0CAP
Bits 5, 4
R
P3.1/T0CK
GND
Bit 3
1/16384
NOTES:
1. During a power-on reset operation, the CPU is idle during the required oscillation
stabilization interval(until bit4 of the basic timer counter overflows
2. It is available only in using internal mode.
Figure 10-7. Basic Timer and Timer 0 Block Diagram
10-9