Flat Panel Television User Manual
Table Of Contents
- TOC
- 01-Overview
- 02-Address Space
- 03-Addressing Modes
- 04-Control Registers
- 05-Interrupt Structure
- 06-Instruction Set
- 07-Clock and Power Circuits
- 08-RESET
- 09-IO PORTS
- 10-BASIC TIMER and TIMER 0
- 11-Timer1
- 12-CounterA
- 13-Timer2
- 14-EMBEDDED Flash Memory Interface
- 15-Low Voltagge Detector
- 16-Electrical Data
- 17-Mechanical Data
- 18-Flash MCU
- 19-Development Tool
- TOC.pdf
S3F80P5_UM_ REV1.00 RESET
STOP ERROR DETECTION & RECOVERY
When RESET Control Bit (smart option bit [0] @ 03FH) is set to ‘0’ and chip is in stop or abnormal state, the
falling edge input of P0 generates the reset signal.
Refer to following table and figure for more information.
Table 8-1. Reset Condition in STOP Mode
Condition
Slope of V
DD
V
DD
Reset
Source
System Reset
Rising up from V
POR
< V
DD
< V
LVD
V
DD
≥ V
LVD
– No system reset
Rising up from V
DD
< V
POR
V
DD
≥ V
LVD
Internal POR System reset occurs
8-7